Non-volatile memory with operation adjustment based on open block ratio and cycling

1 . A non-volatile storage apparatus, comprising:

non-volatile memory cells;

a control line connected to the non-volatile memory cells; and

a control circuit connected to the non-volatile memory cells and the control line, the control circuit is configured to perform a memory operation on the non-volatile memory cells using a parameter that indicates a target voltage for the control line during the memory operation, the control circuit is configured to set the parameter during the memory operation based on an amount of the non-volatile memory cells that have not experienced programming since a last erase process calculated by the control circuit such that the target voltage for the control line during the memory operation is reduced in correlation to the amount of the non-volatile memory cells that have not experienced programming since the last erase process calculated by the control circuit, the control circuit is configured to calculate the amount of the non-volatile memory cells that have not experienced programming since the last erase process based on a combination of measured current used in the non-volatile memory apparatus and an amount of program/erase cycles experienced by the non-volatile memory cells by:

accessing an indication of an amount of program/erase cycles experienced by the non-volatile memory cells stored in the non-volatile storage apparatus,

detecting an amount of current used in the non-volatile storage apparatus while operating the non-volatile memory cells,

calculating a delta as a mathematical function of the indication of the amount of program/erase cycles experienced by the non-volatile memory cells such that the delta changes in correlation to increases in the amount of program/erase cycles experienced by the non-volatile memory cells,

adding the delta to the detected amount of current to create an adjusted current value, and

using the adjusted current value to determine an amount of non-volatile memory cells that have not experienced programming since the last erase process.

2 . The non-volatile storage apparatus of claim 1 , wherein:

the memory operation is a read operation.

3 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus during a read operation.

4 . The non-volatile storage apparatus of claim 1 , wherein:

the memory operation is a first read operation; and

the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus during the first read operation.

5 . The non-volatile storage apparatus of claim 1 , wherein:

the memory operation is a first read operation; and

the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus during the first read operation or a second read operation.

6 . The non-volatile storage apparatus of claim 1 , wherein:

the memory operation is a read operation; and

the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus while ramping up word line voltages during the read operation.

7 . The non-volatile storage apparatus of claim 1 , wherein:

the memory operation is a read operation;

the control circuit is configured to ramp up word line voltages during the read operation by first ramping up word lines to a set of one or more intermediate voltages during the read operation and subsequently ramping up the word lines from the one or more intermediate voltages to one or more target voltages during the read operation; and

the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus during the read operation while ramping up word lines to the set of one or more intermediate voltages and before ramping up the word lines from the one or more intermediate voltages to the one or more target voltages.

8 . The non-volatile storage apparatus of claim 1 , wherein:

the memory operation is a read operation;

the control circuit is configured to ramp up word line voltages during the read operation by first ramping up word lines to a set of one or more intermediate voltages and subsequently ramping up the word lines from the one or more intermediate voltages to one or more target voltages;

the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus during the read operation while ramping up word lines to the set of one or more intermediate voltages during the read operation and before ramping up the word lines from the one or more intermediate voltages to the one or more target voltages; and

the control circuit is configured to perform the read operation by using the one or more parameters set during the read operation based on the determined amount of non-volatile memory cells that have not experienced programming since the last erase process after ramping up word lines to the set of one or more intermediate voltages.

9 . The non-volatile storage apparatus of claim 1 , wherein:

the non-volatile memory cells comprise a block of non-volatile memory cells; and

the control circuit is configured to determine the amount of non-volatile memory cells that have not experienced programming since the last erase process by determining a percentage of the block that has not experienced programming since the last erase process.

10 . The non-volatile storage apparatus of claim 1 , wherein:

the non-volatile memory cells comprise a block of non-volatile memory cells; and

the control circuit is configured to determine the amount of non-volatile memory cells that have not experienced programming since the last erase process by determining a percentage of word lines of the block that have not experienced programming since the last erase process.

11 . The non-volatile storage apparatus of claim 1 , wherein:

the non-volatile memory cells comprise a block of non-volatile memory cells;

the control circuit is configured to determine the amount of non-volatile memory cells that have not experienced programming since the last erase process by determining a percentage of word lines of the block that have not experienced programming since the last erase process;

the memory operation is a first read operation; and

the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus during the first read operation or a second read operation.

12 . The non-volatile storage apparatus of claim 1 , wherein:

the non-volatile memory cells comprise a block of non-volatile memory cells;

the control circuit is configured to determine the amount of non-volatile memory cells that have not experienced programming since the last erase process by determining a percentage of word lines of the block that have not experienced programming since the last erase process;

the memory operation is a read operation;

the control circuit is configured to ramp up word line voltages during the read operation by first ramping up word lines to a set of one or more intermediate voltages and subsequently ramping up the word lines from the one or more intermediate voltages to one or more target voltages;

the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus while ramping up word lines to the set of one or more intermediate voltages and before ramping up the word lines from the one or more intermediate voltages to the one or more target voltages; and

the control circuit is configured to perform the read operation by using the one or more parameters set based on the determined percentage of non-volatile memory cells that have not experienced programming since the last erase process after ramping up word lines to the set of one or more intermediate voltages.

13 . The non-volatile storage apparatus of claim 1 , wherein:

the memory operation is a read operation;

the control line is an unselected word line;

the indicates a target voltage for the unselected word line during the read operation; and

the control circuit is configured to set the target voltage for the unselected word line during the read operation.

14 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit is configured to use the adjusted current value to determine the amount of non-volatile memory cells that have not experienced programming since the last erase process by using the adjusted current value as an index to a data structure that stores percentages correlated to current.

15 . A method, comprising:

accessing an indication of an amount of program/erase cycles experienced by a block of non-volatile memory cells in a non-volatile storage apparatus;

detecting an amount of current in the non-volatile storage apparatus while ramping up word lines during a first read operation for the block of non-volatile memory cells;

adding a delta to the detected amount of current to create an adjusted current value, the delta is based on the indication of an amount of program/erase cycles experienced by the non-volatile memory cells;

using the adjusted current value to determine a percentage of the block that has not experienced programming since a last erase process;

updating one or more read parameters based on the determined percentage of the block that has not experienced programming since a last erase process; and

completing the first read operation including completing the ramping up of word lines using the updated one or more parameters such that one or more word lines are ramped up to a lower target voltage that is reduced in response to the updating of the one or more parameters;

wherein the detecting an amount of current, the adding the delta, the updating one or more read parameters and the completing the first read operation are all performed during the first read operation.

16 . The method of claim 15 , further comprising:

starting the first read operation including ramping up word lines to a set of one or more intermediate voltages, the completing the first read operation includes ramping up the word lines from the one or more intermediate voltages to the target voltage, the detecting an amount of current in the non-volatile storage apparatus comprises detecting the amount of current while ramping up word lines to the set of one or more intermediate voltages and before ramping up the word lines from the one or more intermediate voltages to the target voltage.

17 . The method of claim 16 , wherein:

the updating one or more read parameters comprises setting a magnitude of the target voltage.

18 . The non-volatile storage apparatus of claim 1 , wherein:

the control circuit includes a charge pump; and

the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus while operating the non-volatile memory cells by sensing current at the charge pump during the memory operation.

19 . The non-volatile storage apparatus of claim 1 , further comprising:

a power input connected to the control circuit, the control circuit is configured to detect the amount of current used in the non-volatile storage apparatus while operating the non-volatile memory cells by sensing current at the power input during the memory operation.