Page buffer circuit and peripheral circuit of a memory device
A page buffer circuit of a memory device includes a sensing circuit configured to sense a voltage level of a sensing node changed according to a state of a bit line during a sensing operation. The page buffer circuit also includes a clamping circuit connected to the sensing node, wherein the claiming circuit is configured to control the voltage level of the sensing node not to drop below a clamping level in a predetermined period of the sensing operation.
1 . A page buffer circuit of a memory device, comprising:
a sensing circuit configured to sense a voltage level of a sensing node changed according to a state of a bit line during a sensing operation, the sensing node being connected to the bit line through an intermediate node; and
a clamping circuit connected to the sensing node, the clamping circuit configured to control the voltage level of the sensing node not to drop below a clamping level in a predetermined period of the sensing operation,
wherein the clamping level corresponds to a voltage level at which the intermediate node is pre-charged in a pre-charge period in which the sensing node and the intermediate node are pre-charged.
2 . The page buffer circuit according to claim 1 , wherein the predetermined period includes an evaluation period in which the voltage level of the sensing node drops according to the state of the bit line, and
wherein the clamping circuit, in the evaluation period, is activated when receiving a clamping signal having an enabled level and when the voltage level of the sensing node becomes lower than the clamping level.
3 . The page buffer circuit according to claim 2 , wherein the clamping signal transitions from a disabled level to the enabled level in a pre-charge period in which the sensing node is pre-charged.
4 . The page buffer circuit according to claim 3 , wherein the clamping circuit is deactivated even though the clamping signal has the enabled level when the sensing node is pre-charged in the pre-charge period.
5 . The page buffer circuit according to claim 1 , wherein the clamping circuit includes a transistor including a gate terminal receiving a clamping signal, a source terminal connected to the sensing node, and a drain terminal connected to an operating voltage node.
6 . The page buffer circuit according to claim 5 , wherein an enabled level of the clamping signal is a value obtained by adding a threshold voltage level of the transistor and the clamping level.
7 . The page buffer circuit according to claim 1 , wherein the sensing circuit includes a first connection circuit connecting the bit line to the intermediate node in response to a first connection signal and a second connection circuit connecting the intermediate node to the sensing node in response to a second connection signal.
8 . The page buffer circuit according to claim 1 , wherein the sensing circuit compares the voltage level of the sensing node with a reference level and stores the comparison result therein, and
wherein the clamping level is a voltage level lower than the reference level by a predetermined value.
9 . A page buffer circuit of a memory device, comprising:
a sensing circuit configured to compare a voltage level of a sensing node changed according to a state of a bit line with a reference level and store the comparison result therein; and
a clamping circuit configured to supply a voltage to the sensing node when the voltage level of the sensing node becomes lower than a clamping level lower than the reference level according to the state of the bit line.
10 . The page buffer circuit according to claim 9 , wherein the clamping circuit includes a transistor including a gate terminal receiving a clamping signal, a source terminal connected to the sensing node, and a drain terminal connected to an operating voltage node.
11 . The page buffer circuit according to claim 10 , wherein an enabled level of the clamping signal is a value obtained by adding a threshold voltage level of the transistor and the clamping level.
12 . The page buffer circuit according to claim 9 , wherein the sensing circuit includes a first connection circuit connecting the bit line to an intermediate node in response to a first connection signal and a second connection circuit connecting the intermediate node to the sensing node in response to a second connection signal, and
wherein the clamping level is the same voltage level as a voltage level at which the intermediate node is pre-charged in a pre-charge period in which the sensing node and the intermediate node are pre-charged.
13 . A peripheral circuit of a memory device, comprising:
a page buffer circuit configured to compare a voltage level of a sensing node formed on the basis of a state of a bit line and a clamping signal, with a reference level and store a result of the comparison; and
a control circuit configured to generate the clamping signal and transmit the clamping signal to the page buffer circuit,
wherein the page buffer circuit includes a clamping circuit configured to control the voltage level of the sensing node, based on the clamping signal and the voltage level of the sensing node, so that the voltage level of the sensing node does not drop below a clamping level lower than the reference level.
14 . The peripheral circuit according to claim 13 , wherein the clamping circuit is activated when receiving the clamping signal having an enabled level and when the voltage level of the sensing node becomes lower than the clamping level, in an evaluation period in which the voltage level of the sensing node drops according to the state of the bit line.
15 . The peripheral circuit according to claim 14 , wherein the control circuit transitions the clamping signal from a disabled level to the enabled level in a pre-charge period in which the sensing node is pre-charged.
16 . The peripheral circuit according to claim 15 , wherein the clamping circuit is deactivated even though the clamping signal has the enabled level when the sensing node is pre-charged in the pre-charge period.
17 . The peripheral circuit according to claim 13 , wherein the clamping circuit includes a transistor including a gate terminal receiving the clamping signal, a source terminal connected to the sensing node, and a drain terminal connected to an operating voltage node, and
wherein an enabled level of the clamping signal is a value obtained by adding a threshold voltage level of the transistor and the clamping level.
18 . The peripheral circuit according to claim 13 , wherein the page buffer circuit further includes a first connection circuit connecting the bit line to an intermediate node in response to a first connection signal and a second connection circuit connecting the intermediate node to the sensing node in response to a second connection signal, and
wherein the clamping level is the same voltage level as a voltage level at which the intermediate node is pre-charged in a pre-charge period in which the sensing node and the intermediate node are pre-charged.