IP Library Granted Patent US 12681666
Granted Patent B2
US 12681666 · App. 19/379,624 · Granted Jul 14, 2026

Method and apparatus for improving processing capabilities of a memory controller for error information

Inventor: Yong Xiao (Wuhan, CN)
Assignee: Yangtze Memory Technologies Co., Ltd.
G06F3/0658G06F3/061G06F3/0679
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Quick Facts
Patent No.
US 12681666
App. No.
19/379,624
Granted
Jul 14, 2026
Kind
B2
Abstract

A process of operating a memory controller includes receiving a command to create an input/output (IO) queue. When a first transmission value of the IO queue exceeds a preset value range, target indication information is sent. The target indication information indicates that the first transmission value is invalid. The first transmission value indicates a size of information received by the IO queue.

Claims (112)

1 . A memory system, comprising:

a memory; and

a memory controller, coupled to the memory and configured to:

receive a create input/output (IO) queue command;

create an IO queue according to a first entry size value, wherein the first entry size value is within a preset value range;

send a first indication information indicating that the IO queue is created;

receive a first configuration command after sending the first indication information, wherein the first configuration command instructs the memory controller to configure a second entry size value that exceeds the preset value range;

receive an IO command after receiving the first configuration command; and

execute the IO command based on the IO queue created according to the first entry size value.

2 . The memory system of claim 1 , wherein the memory controller is further configured to:

receive a second configuration command before the create IO queue command is received, wherein the second configuration command instructs the memory controller to configure a third entry size value; and

responsive to the third entry size value exceeding the preset value range, send a second indication information indicating that the third entry size value is invalid.

3 . The memory system of claim 2 , wherein the memory controller is further configured to:

receive a third configuration command instructing the memory controller to configure the first entry size value.

4 . The memory system of claim 2 , wherein the first entry size value, the second entry size value, and the third entry size value indicate a size of each entry in a corresponding IO queue, respectively.

5 . The memory system of claim 1 , wherein the first entry size value comprises a recommended value in a non-volatile memory host controller interface specification (NVMe), and wherein the recommended value is preset and stored in a corresponding memory.

6 . The memory system of claim 1 , wherein the create IO queue command comprises a create IO completion queue command and a create IO submission queue command, the IO queue comprises an IO completion queue and an IO submission queue, the preset value range comprises a first preset value range corresponding to the IO completion queue and a second preset value range corresponding to the IO submission queue, the first entry size value comprises a first value corresponding to the IO completion queue and a second value corresponding to the IO submission queue, the first value is within the first preset value range, the second value is within the second preset value range, and the memory controller is configured to:

receive the create IO completion queue command;

create the IO completion queue according to the first value;

send a first information indicating that the IO completion queue is created;

receive the create IO submission queue command;

create the IO submission queue according to the second value; and

send a second information indicating that the IO submission queue is created.

7 . The memory system of claim 6 , wherein the first preset value range comprises a range between a maximum value and a minimum value of IO completion queue entry size (IOCQES) defined in a non-volatile memory host controller interface specification (NVMe), and the second preset value range comprises a range between a maximum value and a minimum value of IO submission queue entry size (IOSQES) defined in the NVMe.

8 . The memory system of claim 7 , wherein the second entry size value comprises a third value corresponding to the IO completion queue and a fourth value corresponding to the IO submission queue, and wherein the third value exceeds the first preset value range, or the fourth value exceeds the second preset value range.

9 . A memory system, comprising:

a memory; and

a memory controller, coupled to the memory and configured to:

receive a create input/output (IO) queue command;

responsive to a first entry size value exceeding a preset value range, create an IO queue according to a second entry size value, wherein the second entry size value is within the preset value range;

send a first indication information indicating that the IO queue is created;

receive a first configuration command after sending the first indication information, wherein the first configuration command instructs the memory controller to configure a third entry size value that exceeds the preset value range; and

execute an IO command based on the IO queue created according to the second entry size value.

10 . The memory system of claim 9 , wherein the memory controller is further configured to:

receive a second configuration command before the create IO queue command is received, wherein the second configuration command instructs the memory controller to configure the first entry size value; and

responsive to a first entry size value exceeding a preset value range, send a second indication information indicating that the first entry size value is invalid.

11 . The memory system of claim 10 , wherein the memory controller is further configured to:

receive a third configuration command instructing the memory controller to configure the second entry size value.

12 . The memory system of claim 9 , wherein the second entry size value comprises a recommended value in a non-volatile memory host controller interface specification (NVMe), and wherein the recommended value is preset and stored in a corresponding memory.

13 . The memory system of claim 9 , wherein the first entry size value, the second entry size value, and the third entry size value indicate a size of each entry in a corresponding IO queue, respectively.

14 . The memory system of claim 9 , wherein:

the create IO queue command comprises a create IO completion queue command and a create IO submission queue command,

the IO queue comprises an IO completion queue and an IO submission queue,

the preset value range comprises a first preset value range corresponding to the IO completion queue and a second preset value range corresponding to the IO submission queue,

the first preset value range comprises a range between a maximum value and a minimum value of IO completion queue entry size (IOCQES) defined in a non-volatile memory host controller interface specification (NVMe),

the second preset value range comprises a range between a maximum value and a minimum value of IO submission queue entry size (IOSQES) defined in the NVMe,

the second entry size value comprises a first value corresponding to the IO completion queue and a second value corresponding to the IO submission queue,

the first value is within the first preset value range,

the second value is within the second preset value range, and

the memory controller is configured to:

receive the create IO completion queue command;

create the IO completion queue according to the first value;

send a first information indicating that the IO completion queue is created;

receive the create IO submission queue command;

create the IO submission queue according to the second value; and

send a second information indicating that the IO submission queue is created.

15 . An electronic device, comprising:

a memory system, and

a host, coupled to the memory system and configured to:

send, to the memory system, a create input/output (IO) queue command indicating the memory system to create an IO queue;

receive a first indication information indicating that the IO queue is created, wherein the IO queue is created by the memory system according to a first entry size value that is within a preset value range;

send a first configuration command after receiving the first indication information, wherein the first configuration command instructs the memory system to configure a second entry size value that exceeds the preset value range;

send an IO command after sending the first configuration command; and

receive an execution result corresponding to the IO command executed by the memory system based on the IO queue created according to the first entry size value.

16 . The electronic device of claim 15 , wherein the host is further configured to:

send a second configuration command before the create IO queue command is sent, wherein the second configuration command instructs the memory system to configure a third entry size value different with the first entry size value; and

receive a second indication information indicating that the third entry size value is invalid, the second indication information being sent by the memory system responsive to the third entry size value exceeding the preset value range.

17 . The electronic device of claim 16 , wherein the host is further configured to:

in response to receiving the second indication information, send a third configuration command instructing the memory system to configure the first entry size value.

18 . The electronic device of claim 15 , wherein the first entry size value comprises a recommended value in a non-volatile memory host controller interface specification (NVMe).

19 . The electronic device of claim 15 , wherein:

the create IO queue command comprises a create IO completion queue command and a create IO submission queue command,

the IO queue comprises an IO completion queue and an IO submission queue,

the preset value range comprises a first preset value range corresponding to the IO completion queue and a second preset value range corresponding to the IO submission queue,

the first preset value range comprises a range between a maximum value and a minimum value of IO completion queue entry size (IOCQES) defined in a non-volatile memory host controller interface specification (NVMe),

the second preset value range comprises a range between a maximum value and a minimum value of IO submission queue entry size (IOSQES) defined in the NVMe,

the first entry size value comprises a first value corresponding to the IO completion queue and a second value corresponding to the IO submission queue,

the first value is within the first preset value range, the second value is within the second preset value range, and

the host is configured to:

send the create IO completion queue command;

receive a first information indicating that the IO completion queue is created,

wherein the IO completion queue is created according to the first value;

send the create IO submission queue command; and

receive a second information indicating that the IO submission queue is created, wherein the IO submission queue is created according to the second value.

20 . A method of operating memory system comprising a memory controller, comprising:

receiving, by the memory controller, a create input/output (IO) queue command;

creating, by the memory controller, an IO queue according to a first entry size value, wherein the first entry size value is within a preset value range;

sending, by the memory controller, a first indication information indicating that the IO queue is created;

receiving, by the memory controller, a first configuration command after sending the first indication information, wherein the first configuration command instructs the memory controller to configure a second entry size value that exceeds the preset value range;

receiving an IO command after receiving the first configuration command; and

executing, by the memory controller, the IO command based on the IO queue created according to the first entry size value.

21 . The method of claim 20 , further comprising:

receiving, by the memory controller, a second configuration command before the create IO queue command is received, wherein the second configuration command instructs the memory controller to configure a third entry size value; and

responsive to the third entry size value exceeding the preset value range, sending, by the memory controller, a second indication information indicating that the third entry size value is invalid.

22 . The method of claim 21 , further comprising:

receiving, by the memory controller, a third configuration command instructing the memory controller to configure the first entry size value.

23 . The method of claim 20 , wherein the first entry size value comprises a recommended value in a non-volatile memory host controller interface specification (NVMe), and wherein the recommended value is preset and stored in a corresponding memory.

24 . The method of claim 20 , wherein:

the create IO queue command comprises a create IO completion queue command and a create IO submission queue command,

the IO queue comprises an IO completion queue and an IO submission queue,

the preset value range comprises a first preset value range corresponding to the IO completion queue and a second preset value range corresponding to the IO submission queue,

the first entry size value comprises a first value corresponding to the IO completion queue and a second value corresponding to the IO submission queue,

the first value is within the first preset value range,

the second value is within the second preset value range, and

the method comprises:

receiving the create IO completion queue command;

creating the IO completion queue according to the first value;

sending a first information indicating that the IO completion queue is created;

receiving the create IO submission queue command;

creating the IO submission queue according to the second value; and

sending a second information indicating that the IO submission queue is created.

25 . The method of claim 24 , wherein the first preset value range comprises a range between a maximum value and a minimum value of IO completion queue entry size (IOCQES) defined in a non-volatile memory host controller interface specification (NVMe), and the second preset value range comprises a range between a maximum value and a minimum value of IO submission queue entry size (IOSQES) defined in the NVMe.