Managing retention latency for memory devices of vehicle systems

1 . A method comprising:

receiving a set of data bits from a host;

writing an original time stamp for the set of data bits;

writing the set of data bits to a first location in memory;

computing a time difference between a current time and the original time stamp;

determining a time range of a plurality of time ranges using the time difference;

selecting a set of trim settings using the time range;

reading the set of data bits from the first location in memory using the set of trim settings;

writing the set of data bits to a second location in memory;

generating an updated time stamp representing a time of writing the set of data bits to the second location in memory;

computing a second time difference between the original time stamp and the current time;

determining that the second time difference satisfies a threshold time difference; and

writing the set of data bits to a third location in memory using a first type of programming in response to the determination, wherein writing the set of data bits to the third location occurs after writing the set of data bits to the second location.

2 . The method of claim 1 , wherein writing the set of data bits to the second location in memory comprises:

determining the time difference does not satisfy a threshold time difference; and

writing the set of data bits to the second location in memory using a second type of programming.

3 . The method of claim 2 , wherein the second type of programming comprises programming the set of data bits using a second set of write trim settings for short retention latency.

4 . The method of claim 1 , wherein writing the set of data bits to the second location in memory comprises:

determining the time difference satisfies a threshold time difference; and

writing the set of data bits to the second location in memory using the first type of programming.

5 . The method of claim 4 , wherein the first type of programming comprises programming the set of data bits using a first set of write trim settings for long retention latency.

6 . The method of claim 1 further comprising:

receiving a read request for the set of data bits from the second location in memory;

computing a third time difference between the updated time stamp and the current time;

determining a second time range of the plurality of time ranges using the third time difference;

selecting a second set of trim settings using the second time range; and

reading the set of data bits from the second location in memory using the second set of trim settings.

7 . The method of claim 1 , wherein selecting the set of trim settings further uses a number of program/erase cycles.

8 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

receive a set of data bits from a host;

write an original time stamp for the set of data bits;

write the set of data bits to a first location in memory;

compute a time difference between a current time and the original time stamp;

determine a time range of a plurality of time ranges using the time difference;

select a set of trim settings using the time range;

read the set of data bits from the first location in memory using the set of trim settings;

write the set of data bits to a second location in memory;

generate an updated time stamp representing a time of writing the set of data bits to the second location in memory;

compute a second time difference between the original time stamp and the current time;

determine that the second time difference satisfies a threshold time difference; and

write the set of data bits to a third location in memory using a first type of programming in response to the determination, wherein writing the set of data bits to the third location occurs after writing the set of data bits to the second location.

9 . The non-transitory computer-readable storage medium of claim 8 , wherein writing the set of data bits to the second location in memory comprises:

determining the time difference does not satisfy a threshold time difference; and

writing the set of data bits to the second location in memory using a second type of programming.

10 . The non-transitory computer-readable storage medium of claim 9 , wherein the second type of programming comprises programming the set of data bits using a second set of write trim settings for short retention latency.

11 . The non-transitory computer-readable storage medium of claim 9 , wherein writing the set of data bits to the second location in memory comprises:

determining the time difference satisfies a threshold time difference; and

writing the set of data bits to the second location in memory using the first type of programming.

12 . The non-transitory computer-readable storage medium of claim 11 , wherein the first type of programming comprises programming the set of data bits using a first set of write trim settings for long retention latency.

13 . The non-transitory computer-readable storage medium of claim 8 wherein selecting the set of trim settings further uses a number of program/erase cycles.

14 . The non-transitory computer-readable storage medium of claim 9 , wherein the processing device is further to:

receive a read request for the set of data bits from the second location in memory;

compute a third time difference between the updated time stamp and the current time;

determine a second time range of the plurality of time ranges using the third time difference;

select a second set of trim settings using the second time range; and

read the set of data bits from the second location in memory using the second set of trim settings.

15 . A system comprising:

a plurality of memory devices; and

a processing device, operatively coupled with the plurality of memory devices, the processing device comprising a processor configured to execute instructions to cause the processing device to:

receive a set of data bits from a host;

write an original time stamp for the set of data bits;

write the set of data bits to a first location in memory;

compute a time difference between a current time and the original time stamp;

determine a time range of a plurality of time ranges using the time difference;

select a set of trim settings using the time range and a number of program/erase cycles;

read the set of data bits from the first location in memory using the set of trim settings;

write the set of data bits to a second location in memory;

generate an updated time stamp representing a time of writing the set of data bits to the second location in memory;

compute a second time difference between the original time stamp and the current time;

determine that the second time difference satisfies a threshold time difference; and

write the set of data bits to a third location in memory using a first type of programming in response to the determination, wherein writing the set of data bits to the third location occurs after writing the set of data bits to the second location.

16 . The system of claim 15 , wherein writing the set of data bits to the second location in memory comprises:

determining the time difference does not satisfy a threshold time difference; and

writing the set of data bits to the second location in memory using a second type of programming.

17 . The system of claim 16 , wherein the second type of programming comprises programming the set of data bits using a second set of write trim settings for short retention latency.

18 . The system of claim 15 , wherein writing the set of data bits comprises:

determining the time difference satisfies a threshold time difference; and

writing the set of data bits to the second location in memory using the first type of programming.

19 . The system of claim 18 , wherein the first type of programming comprises programming the set of data bits using a first set of write trim settings for long retention latency.

20 . The system of claim 15 , wherein the processing device is further to:

receive a read request for the set of data bits from the second location in memory;

compute a third time difference between the updated time stamp and the current time;

determine a second time range of the plurality of time ranges using the third time difference;

select a second set of trim settings using the second time range; and

read the set of data bits from the second location in memory using the second set of trim settings.