Systolic array with parallel output rounding

1 . A systolic array processor configured to perform matrix multiplication between two input matrices and provide, as a result, a set of 32-bit values, wherein the systolic array processor comprises:

a rounder configured to perform a set of stochastic rounding operations to stochastically round individual 32-bit values of the set of 32-bit values to result in a set of 16-bit outputs, wherein individual stochastic rounding operations of the set of stochastic rounding operations rely on individual pseudo-random numbers of a set of pseudo-random numbers, wherein the rounder comprises:

a plurality of maximal length linear feedback shift registers (LFSRs) configured to deterministically generate the set of pseudo-random numbers, wherein each maximal length LFSR is associated with a pseudo-random number sequence and is configured to generate a next pseudo-random number in the pseudo-random number sequence based on a state value representing a position within the pseudo-random number sequence,

wherein, to generate the set of pseudo-random numbers, each maximal length LFSR is configured, for each subset of the set of pseudo-random numbers, to:

assume a state matching a current state value from a state value store shared among the plurality of maximal length LFSRs; and

cycle through a number of positions within the pseudo-random number sequence based on a relative position of the maximal length LFSR among the plurality of maximal length LFSRs to arrive at a resultant pseudo-random number to be included within the set of pseudo-random numbers,

wherein a final maximal length LFSR of the plurality of maximal length LFSRs is configured, for each subset of the set of pseudo-random numbers, to update the current state value of the state value store with a state of the final maximal length LFSR.

2 . The systolic array processor of claim 1 , wherein the systolic array processor further comprises a multiplexer configured to select the final maximal length LFSR from the plurality of maximal length LFSRs.

3 . The systolic array processor of claim 1 , wherein the rounder is further configured to generate rounded 32-bit values based on performing the set of stochastic rounding operations, wherein the systolic array processor further comprises a trailing bit reducer configured to:

reduce a quantity of bits representing significands of 32-bit values, and

generate 16-bit values based on reducing the quantity of bits representing the significands of the 32-bit values.

4 . The systolic array processor of claim 1 , wherein the rounder is further configured to select the plurality of maximal length LFSRs from a set of maximal length LFSRs based on a quantity of the plurality of maximal length LFSRs matching a selected number of parallel stochastic rounding operations.

5 . An integrated circuit comprising:

a rounder configured to:

receive a first number:

select a first random number generator from a plurality of random number generators based on a first relative numerical position of the first random number generator among the plurality of random number generators, wherein the plurality of random number generators are associated with a random number sequence and are configured to generate a next random number in the random number sequence based on a respective state value representing a position within the random number sequence, wherein each of the plurality of random number generators is configured to:

assume a state based on a current state value from a state value store shared among the plurality of random number generators, and

cycle through a number of positions within the random number sequence corresponding to a relative numerical position of the random number generator among the plurality of random number generators to arrive at a resultant random number, wherein each random number generator of the plurality of random number generators is initialized with the same state value and cycled through a different number of state values after the same state value; and

perform a rounding operation to round the first number based on a resultant random number generated by the first random number generator.

6 . The integrated circuit of claim 5 , wherein the rounder is further configured to generate one or more rounded numbers based on performing the rounding operation, wherein the integrated circuit further comprises a trailing bit reducer configured to:

reduce a quantity of bits representing the one or more rounded numbers, and

generate one or more reduced numbers based on reducing the quantity of bits representing the one or more rounded numbers.

7 . The integrated circuit of claim 5 , wherein the rounder is further configured to select the plurality of random number generators from a set of random number generators based on a quantity of the plurality of random number generators matching a selected number of parallel rounding operations.

8 . The integrated circuit of claim 5 , wherein a final random number generator of the plurality of random number generators is configured to update the current state value of the state value store with a state of a final random number generator of the plurality of random number generators.

9 . The integrated circuit of claim 8 , wherein the integrated circuit further comprises a multiplexer configured to select the final random number generator from the plurality of random number generators.

10 . The integrated circuit of claim 8 , wherein the rounder obtains an updated state value, wherein the integrated circuit further comprises a multiplexer configured to select the state of the final random number generator or the updated state value.

11 . The integrated circuit of claim 8 , wherein the rounder obtains an updated state value, wherein the rounder is configured to update the current state value of the state value store with the updated state value.

12 . The integrated circuit of claim 5 , wherein the rounding operation comprises a stochastic rounding operation.

13 . The integrated circuit of claim 5 , wherein each of the plurality of random number generators is configured to generate one or more pseudo-random numbers, wherein the resultant random number generated by the first random number generator comprises a pseudo-random number.

14 . The integrated circuit of claim 5 , wherein:

the rounder is further configured to convert an input floating-point number to an output floating-point number by reducing a number of significand bits in the input floating-point number to result in the output floating-point number, the output floating-point number having fewer significand bits than the input floating-point number.

15 . The integrated circuit of claim 5 , wherein:

the rounder is further configured to convert an input floating-point number to an output floating-point number by reducing a number of significand bits in the input floating-point number to result in the output floating-point number, the output floating-point number having fewer significand bits than the input floating-point number,

wherein a processing element of a set of processing elements is configured to receive as input numbers matching a bit format of the output floating-point number.

16 . The integrated circuit of claim 5 , wherein:

the rounder is further configured to convert an input floating-point number to an output floating-point number by reducing a number of significand bits in the input floating-point number to result in the output floating-point number, the output floating-point number having fewer significand bits than the input floating-point number,

wherein a processing element of a set of processing elements is configured to output floating point numbers matching a bit format of the input floating-point number.

17 . The integrated circuit of claim 5 , wherein the rounding operation is a first rounding operation, wherein the rounder is further configured to:

receive a second number;

select a second random number generator from a plurality of random number generators; and

perform a second rounding operation to round the second number based on a resultant random number generated by the second random number generator.

18 . The integrated circuit of claim 5 , wherein to select the first random number generator, the rounder is further configured to select the first random number generator further based on:

a relative position of the first number in a set of numbers being rounded in parallel.

19 . A method, comprising:

receiving a first number;

identifying a first random number generator of a plurality of random number generators based on a first relative numerical position of the first random number generator among the plurality of random number generators, wherein each of the plurality of random number generators is associated with a random number sequence and is configured to generate a next random number in the random number sequence based on a respective state value representing a position within the random number sequence, wherein each of the plurality of random number generators is configured to assume a state based on current state value shared among the plurality of random number generators and cycle through a number of positions within the random number sequence corresponding to a relative numerical position of the random number generator among the plurality of random number generators to arrive at a resultant random number, wherein each random number generator of the plurality of random number generators is initialized with the same state value and cycled through a different number of state values after the same state value; and

performing a rounding operation to round the first number based on a resultant random number generated by the first random number generator.

20 . The method of claim 19 , further comprising selecting the plurality of random number generators from a set of random number generators based on a quantity of the plurality of random number generators matching a selected number of parallel rounding operations.