Weight stationary in-memory-computing neural network accelerator with localized data multiplexing
Systems, apparatuses, and methods include technology that identifies that a first memory cell of a plurality of memory cells stores data that is associated with a multiply-accumulate operation. The plurality of memory cells is associated with a multiply-accumulator (MAC). The technology executes a connection operation to electrically connect the first memory cell to the MAC to execute the multiply-accumulate operation. A second memory cell of the plurality of memory cells is electrically disconnected from the MAC during the multiply-accumulate operation. The technology executes, with the MAC, the multiply-accumulate operation based on the data.
1 . A computing system comprising:
a plurality of memory cells;
a charge domain multiply-accumulator that includes a plurality of capacitors; and
a controller implemented in one or more of configurable logic or fixed-functionality logic hardware, wherein the controller is to:
identify that a first memory cell of the plurality of memory cells stores data that is associated with a charge domain multiply-accumulate operation, wherein the first memory cell comprises first latches to store the data, a first switch controlled by a first control signal, and a first inverter between the first latches and the first switch;
execute a connection operation to electrically connect the first memory cell to the charge domain multiply-accumulator to execute the charge domain multiply-accumulate operation by applying the first control signal to the first switch, wherein a second memory cell of the plurality of memory cells is electrically disconnected from the charge domain multiply-accumulator during the charge domain multiply-accumulate operation; and
execute, with the charge domain multiply-accumulator, the charge domain multiply-accumulate operation based on the data.
2 . The computing system of claim 1 , wherein the charge domain multiply-accumulate operation is to include a generation, with the charge domain multiply-accumulator, of a first analog signal based on multibit computation operations that are executed based on the data.
3 . The computing system of claim 1 , wherein:
the second memory cell comprises second latches, a second switch controllable by a second control signal, and a second inverter between the second latches and the second switch; and
the controller is further to: apply the second control signal to the second switch during the charge domain multiply-accumulate operation.
4 . The computing system of claim 3 , further comprising a common read bit conductor that electrically connects to the charge domain multiply-accumulator and is associated with the plurality of memory cells;
wherein:
the first switch is to selectively electrically connect the first inverter to the common read bit conductor; and
the second switch is to selectively electrically connect the second inverter to the common read bit conductor.
5 . The computing system of claim 3 , wherein:
a side of the first latches is connected to an input of the first inverter;
the first switch selectively connects an output of the first inverter to a common read bit line according to the first control signal; and
the second switch selectively connects the second inverter to the common read bit line according to the second control signal.
6 . The computing system of claim 3 , wherein the first switch and the second switch form a multiplexer.
7 . The computing system of claim 1 , wherein the data is weight data associated with a neural network operation.
8 . The computing system of claim 1 , wherein the first inverter is to electrically isolate the first memory cell from noise.
9 . The computing system of claim 1 , wherein the plurality of memory cells is a static random-access memory, a dynamic random-access memory, a magnetoresistive random-access memory, or a phase-change memory.
10 . The computing system of claim 1 , wherein the charge domain multiply-accumulator includes a C-2C ladder that includes the plurality of capacitors.
11 . The computing system of claim 1 , wherein:
the first latches include four transistors;
the first inverter includes two transistors; and
the first switch includes one transistor.
12 . The computing system of claim 1 , wherein:
the plurality of capacitors are Metal-Oxide-Metal capacitors placed on top of the first memory cell and the second memory cell.
13 . The computing system of claim 1 , wherein:
the plurality of capacitors include a plurality of branches;
each branch has a branch switch controllable by a bit and a branch capacitor; and
at least one serial capacitor inserted between two branches of the plurality of branches.
14 . The computing system of claim 13 , wherein:
the branch capacitor has one unit capacitance; and
a serial capacitor of the at least one serial capacitor has two unit capacitances.
15 . The computing system of claim 1 , wherein the charge domain multiply-accumulator is to receive an input activation signal of a neural network.
16 . An in-memory computing system, comprising:
a charge domain multiply-accumulator that includes a plurality of capacitors;
a common read bit conductor that is electrically connected to the charge domain multiply-accumulator; and
a memory array including a first memory cell and a second memory cell;
wherein:
the first memory cell comprises first latches, a first transistor, and a first inverter between the first latches and the first transistor;
the second memory cell comprises second latches, a second transistor, and a second inverter between the second latches and the second transistor;
the first transistor is to selectively connect a first output of the first inverter to the common read bit conductor; and
the second transistor is to selectively connect a second output of the second inverter to the common read bit conductor.
17 . The in-memory computing system of claim 16 , further comprising:
a controller, implemented at least partly in one or more of configurable logic or fixed-functionality logic hardware, to:
identify that the first memory cell stores data that is associated with a charge domain multiply-accumulate operation;
control the first transistor to electrically connect the first memory cell to the charge domain multiply-accumulator via the common read bit conductor; and
control the second transistor to electrically disconnect the second memory cell from the charge domain multiply-accumulator during execution of the charge domain multiply-accumulate operation.
18 . The in-memory computing system of claim 17 , further comprising:
a first local read word line to carry a first signal to control the first transistor; and
a second local read word line to carry a second signal to control the second transistor.
19 . The in-memory computing system of claim 17 , wherein the charge domain multiply-accumulator is configured to execute the charge domain multiply-accumulate operation using a C-2C ladder that includes the plurality of capacitors.
20 . The in-memory computing system of claim 19 , wherein the charge domain multiply-accumulate operation is to include a generation, with the charge domain multiply-accumulator, of a first analog signal based on multibit computation operations that are executed based on the data.
21 . The in-memory computing system of claim 16 , wherein the first inverter and the second inverter are to electrically isolate the first memory cell and the second memory cell from noise on the common read bit conductor.
22 . The in-memory computing system of claim 21 , wherein the first memory cell includes at least nine transistors and the second memory cell includes at least nine transistors.
23 . The in-memory computing system of claim 16 , wherein the first transistor and the second transistor form a multiplexer.
24 . A method for performing a charge domain multiply-accumulate operation:
identifying, by a controller implemented in one or more of configurable logic or fixed-functionality logic hardware, that a first memory cell of a plurality of memory cells stores data that is associated with the charge domain multiply-accumulate operation, wherein the first memory cell comprises first latches to store the data, a first switch controlled by a first control signal, and a first inverter between the first latches and the first switch;
applying, by the controller on a first local read word line, the first control signal to the first switch to electrically connect the first memory cell to a common read bit line connected to a charge domain multiply-accumulator, wherein the charge domain multiply-accumulator has a C-2C ladder;
applying, by the controller on a second local read word line, a second control signal to a second switch of a second memory cell of the plurality of memory cells to electrically disconnect the second memory cell from the common read bit line connected to the charge domain multiply-accumulator; and
executing, by the charge domain multiply-accumulator, the charge domain multiply-accumulate operation based on the data.
25 . The method of claim 24 , wherein executing the charge domain multiply-accumulate operation based on the data comprises:
generating, with the charge domain multiply-accumulator, a first analog signal based on multibit computation operations that are executed based on the data.