Selecting intermediate representation transformations for compilations

Inventors: Emily Anne Furst (Duvall, WA); Robin Conradine Knauerhase (Portland, OR); Sangeeta Chowdhary (Sunnyvale, CA); Michael L Chu (San Jose, CA)

Assignee: Advanced Micro Devices, Inc.

G06F8/41

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Quick Facts

Patent No.: US 12681700
App. No.: 18/342,347
Granted: Jul 14, 2026
Kind: B2

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Abstract

Selecting intermediate representation transformation for compilations is described. In accordance with the described techniques, source code is received to be compiled by a compilation system for execution by a processor of hardware. Intermediate representation transformations are selected for the source code based on system load information associated with the hardware. The intermediate representation transformations are output to the compilation system.

Claims (34)

1 . A system comprising:

hardware having a particular configuration;

decision circuitry to:

receive a set of previously output intermediate representation transformations for source code representing a path through a multi-level intermediate representation (MLIR) structure that includes dialects at multiple levels, wherein a transition between the dialects at different levels of the MLIR structure represents an intermediate representation transformation of the source code; and

output different intermediate representation transformations for the source code based on the particular configuration of the hardware by selecting a different path through the MLIR structure, the different path including a dialect representing a system resource selected in response to the system resource becoming available; and

compilation circuitry to compile the source code into machine code using the different intermediate representation transformations.

2 . The system of claim 1 , wherein the decision circuitry is further configured to output the different intermediate representation transformations based on system load characteristics associated with the hardware.

3 . The system of claim 1 , wherein the decision circuitry is further configured to output the different intermediate representation transformations based on an estimated availability of a processor to execute the machine code produced from the source code.

4 . The system of claim 1 , wherein the decision circuitry is further configured to output the different intermediate representation transformations based on a cost model that estimates program costs associated with the different intermediate representation transformations.

5 . The system of claim 4 , wherein the decision circuitry is configured to iteratively output the different intermediate representation transformations based on a program cost associated with a previously selected intermediate representation transformation for the source code.

6 . The system of claim 4 , wherein the decision circuitry is configured to estimate a program cost associated with an intermediate representation by summing costs of operators included in a particular dialect associated with the intermediate representation.

7 . The system of claim 1 , wherein the different intermediate representation transformations are selected from a group of predefined intermediate representation transformations.

8 . The system of claim 1 , further comprising a processor to execute the machine code produced from the source code, the processor including at least one of a central processing unit, a graphics processing unit, or an accelerated processing unit.

9 . The system of claim 1 , wherein the different intermediate representation transformations include a previously output intermediate representation transformation from the set, the previously output intermediate representation transformation selected based on at least one of a program cost estimated by a cost model of the decision circuitry, a change in system load characteristics associated with the hardware, or a reconfiguration of the hardware.

10 . The system of claim 1 , wherein the decision circuitry is further configured to output the different intermediate representation transformations based on metadata describing the previously output intermediate representation transformations for the source code.

11 . The system of claim 1 , wherein the hardware reconfigures from a first configuration to the particular configuration.

12 . The system of claim 1 , wherein the different path includes at least one of the previously output intermediate representation transformations.

13 . The system of claim 1 , wherein the set of previously output intermediate representation transformations is selected before the system resource becomes available, and the different intermediate representation transformations are selected while the system resource is available.

14 . The system of claim 1 , wherein the decision circuitry is configured to output the different intermediate representation transformations by reverting to a previous state of compilation representing an intermediate level of the path through the MLIR structure.

15 . The system of claim 1 , wherein the dialect is a hardware-specific dialect representing a processor of the hardware.

16 . A method comprising:

receiving source code to be compiled by compilation circuitry for execution by hardware having a particular configuration;

receiving a set of previously output intermediate representation transformations for the source code representing a path through a multi-level intermediate representation (MLIR) structure that includes dialects at multiple levels, wherein a transition between the dialects at different levels of the MLIR structure represents an intermediate representation transformation of the source code;

compiling, by the compilation circuitry, the source code into machine code using the different intermediate representation transformations.

17 . The method of claim 16 , wherein the set of previously output intermediate representation transformations is selected before the system resource becomes available.

18 . A method comprising:

receiving source code to be compiled by compilation circuitry for execution by hardware;

reconfiguring the hardware from a first configuration to a second configuration;

receiving first intermediate representation transformations for the source code representing a path through a multi-level intermediate representation (MLIR) structure that includes dialects at multiple levels, wherein a transition between the dialects at different levels of the MLIR structure represents an intermediate representation transformation of the source code, and the first intermediate representation transformations are associated with the first configuration;

outputting second intermediate representation transformations for the source code based on the second configuration of the hardware by selecting a different path through the MLIR structure, the different path including a dialect representing a system resource selected in response to the system resource becoming available; and

compiling, by the compilation circuitry, the source code into machine code using the second intermediate representation transformations.

19 . The method of claim 18 , wherein the second intermediate representation transformations include a previously output intermediate representation transformation of the first intermediate representation transformations for the source code.

20 . The method of claim 19 , wherein the previously output intermediate representation transformation for the source code is selected based on at least one of a program cost estimated by a cost model, a change in system load characteristics associated with the hardware, or a reconfiguration of the hardware.