Scalable hardware FIFO

1 . A system, comprising:

a first-in-first-out (FIFO) device comprising:

a plurality of FIFO stages coupled in series, wherein each of the FIFO stages includes:

a data register representing a FIFO entry;

a valid register operable to store a data valid signal to provide a valid signal indicating whether the data register of a corresponding FIFO stage is storing valid data; and

a control circuit operable to generate the data valid signal for the corresponding FIFO stage, and a load signal to control data loading into the data register of the corresponding FIFO stage,

wherein the control circuit of each intermediate FIFO stage having a preceding FIFO stage and a subsequent FIFO stage is operable to generate the load signal based on:

valid signals of the intermediate FIFO stage, the preceding FIFO stage, and the subsequent FIFO stage;

a push signal to load input data into the FIFO device; and

a pop signal to provide output data from the FIFO device, and

wherein the control circuit of each intermediate FIFO stage having the preceding FIFO stage and the subsequent FIFO stage is further operable to generate the data valid signal for the corresponding FIFO stage when:

the push signal is asserted, and the valid signal of the preceding FIFO stage indicates that valid data is stored in the preceding FIFO stage, or

the pop signal is asserted, and the valid signal of the subsequent FIFO stage indicates that valid data is stored in the subsequent FIFO stage;

a source device operable to:

send the input data to the FIFO device when the FIFO device is not full as indicated by a vector of valid signals corresponding to the FIFO stages; and

assert the push signal to load the input data into the FIFO device; and

a target device operable to:

assert the pop signal when ready to read the output data from the FIFO device, and the FIFO device is not empty as indicated by the vector of valid signals corresponding to the FIFO stages; and

receive the output data from the FIFO device.

2 . The system of claim 1 , wherein an asserted state of the valid signal of a last FIFO stage at an input of the FIFO device is used to indicate that the FIFO device is full.

3 . The system of claim 1 , wherein a de-asserted state of the valid signal of a first FIFO stage at an output of the FIFO device is used to indicate that the FIFO device is empty.

4 . The system of claim 1 , wherein the output data is read from a data register corresponding to a first FIFO stage having only a subsequent FIFO stage, but not a preceding FIFO stage.

5 . A first-in-first-out (FIFO) device, comprising:

a plurality of FIFO stages coupled in series, wherein each of the FIFO stages includes:

a data register representing a FIFO entry;

a valid register operable to store a data valid signal to provide a valid signal indicating whether the data register of a corresponding FIFO stage is storing valid data; and

a control circuit operable to generate the data valid signal for the corresponding FIFO stage, and a load signal to control data loading into the data register of the corresponding FIFO stage,

wherein the control circuit of each intermediate FIFO stage having a preceding FIFO stage and a subsequent FIFO stage is operable to generate the load signal based on:

valid signals of the intermediate FIFO stage, the preceding FIFO stage, and the subsequent FIFO stage;

a push signal to load input data into the FIFO device; and

a pop signal to provide output data from the FIFO device, and

wherein the control circuit of each intermediate FIFO stage having the preceding FIFO stage and the subsequent FIFO stage is further operable to generate the data valid signal for the corresponding FIFO stage when:

the push signal is asserted, and the valid signal of the preceding FIFO stage indicates that valid data is stored in the preceding FIFO stage, or

the pop signal is asserted, and the valid signal of the subsequent FIFO stage indicates that valid data is stored in the subsequent FIFO stage.

6 . The FIFO device of claim 5 , wherein each FIFO stage that has a subsequent FIFO stage includes:

an input multiplexer to select between the input data to the FIFO device and data stored in a data register of the subsequent FIFO stage to provide the data for loading into a data register of the FIFO stage.

7 . The FIFO device of claim 6 , wherein the input multiplexer selects the data stored in the data register of the subsequent FIFO stage to provide the data for loading into the data register of the FIFO stage when a valid signal of the subsequent FIFO stage indicates that the data register of the subsequent FIFO stage is storing valid data.

8 . The FIFO device of claim 5 , wherein the load signal of each FIFO stage is asserted to load the data into the FIFO stage when:

the valid signal of the FIFO stage indicates that the valid data is stored in the FIFO stage, the pop signal is asserted, and the push signal is asserted.

9 . The FIFO device of claim 5 , wherein the load signal of each FIFO stage that has a subsequent FIFO stage is asserted to load data into the FIFO stage when:

the valid signal of the subsequent FIFO stage indicates that valid data is stored in the subsequent FIFO stage, and the pop signal is asserted.

10 . The FIFO device of claim 5 , wherein the load signal of each FIFO stage that has a preceding FIFO stage is asserted to load data into the FIFO stage when:

the valid signal of the FIFO stage indicates no valid data is stored in the FIFO stage, the valid signal of the preceding FIFO stage indicates that valid data is stored in the preceding FIFO stage, the pop signal is not asserted, and the push signal is asserted.

11 . The FIFO device of claim 5 , wherein a control circuit of a first FIFO stage having only a subsequent FIFO stage is operable to generate a data valid signal for the first FIFO stage when:

the push signal is asserted, and a valid signal of the first FIFO stage indicates that no valid data is stored in the first FIFO stage, or

a valid signal of the subsequent FIFO stage indicates that valid data is stored in the subsequent FIFO stage.

12 . The FIFO device of claim 5 , wherein a control circuit of a last FIFO stage having only a preceding FIFO stage is operable to generate a data valid signal for the last FIFO stage when:

the push signal is asserted, a valid signal of the last FIFO stage indicates that no valid data is stored in the last FIFO stage, and a valid signal of the preceding FIFO stage indicates that valid data is stored in the preceding FIFO stage.

13 . The FIFO device of claim 5 , wherein asserted valid bits of a valid vector formed by valid signals corresponding to the FIFO stages are stacked towards a first FIFO stage at an output of the FIFO device.

14 . The FIFO device of claim 5 , wherein an asserted state of the valid signal of a last FIFO stage at an input of the FIFO device is used to indicate that the FIFO device is full.

15 . The FIFO device of claim 5 , wherein a de-asserted state of the valid signal of a first FIFO stage at an output of the FIFO device is used to indicate that the FIFO device is empty.

16 . A method, comprising:

receiving a push signal to store input data into a first-in-first-out (FIFO) device comprising a plurality of FIFO stages coupled in series, wherein each of the FIFO stages includes a data register representing a FIFO entry, a valid register to store a data valid signal to provide a valid signal indicating whether the FIFO entry is storing valid data, and an input multiplexer to provide to a FIFO stage;

upon receiving the push signal, determining by the FIFO stage of the FIFO device whether to update the data register of the FIFO stage based on respective valid signals from the FIFO stage, and neighboring FIFO stages of the FIFO stage; and

upon receiving a pop signal to provide output data from the FIFO device, determining by the FIFO stage whether to provide data stored in the data register of the FIFO stage to the preceding FIFO stage based on the valid signal from the FIFO stage, wherein a control circuit of each intermediate FIFO stage having a preceding FIFO stage and a subsequent FIFO stage generates the data valid signal for the corresponding FIFO stage when:

the push signal is asserted, and the valid signal of the preceding FIFO stage indicates that valid data is stored in the preceding FIFO stage, or

the pop signal is asserted, and the valid signal of the subsequent FIFO stage indicates that valid data is stored in the subsequent FIFO stage.

17 . The method of claim 16 , wherein, upon receiving the pop signal, the input multiplexer of the FIFO stage selects the data stored in the data register of the subsequent FIFO stage to provide to the FIFO stage if the valid signal from the subsequent FIFO stage is asserted.

18 . The method of claim 16 , further comprising using the valid signal of a last FIFO stage at an input of the FIFO device as a FIFO full signal.

19 . The method of claim 16 , further comprising inverting the valid signal of a first FIFO stage at an output of the FIFO device as a FIFO empty signal.