Processor performance management for pre-boot applications

1 . An Information Handling System (IHS), comprising:

a processor; and

a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution, cause the IHS to:

perform a data download operation in a preboot environment, wherein the preboot environment comprises a Basic Input/Output System (BIOS) application; and

modify a frequency or speed of the processor based, at least in part, upon an amount of downloaded data;

wherein to modify the frequency or speed, the BIOS application is configured to send a command to an Embedded Controller (EC) coupled to the processor, and wherein the command instructs the EC to set the processor to a higher power level; and

wherein to modify the frequency or speed, the BIOS application is further configured to enforce a policy, and wherein the policy indicates a minimum amount of the downloaded data to trigger the modification.

2 . The IHS of claim 1 , wherein the data download operation is performed during a Boot Device Selection (BDS) phase of a boot sequence.

3 . The IHS of claim 1 , wherein the command instructs the EC to increase the frequency or speed.

4 . The IHS of claim 3 , wherein the increase is based on the amount.

5 . The IHS of claim 1 , wherein the policy further indicates, for a first amount, a first modification to the frequency or speed and, for a second amount, a second modification to the frequency or speed.

6 . The IHS of claim 1 , wherein the program instructions, upon execution, cause the IHS to validate an entitlement or license associated with the IHS or user of the IHS prior to the modification.

7 . The IHS of claim 1 , wherein the downloaded data comprises a recovery image.

8 . The IHS of claim 7 , wherein the program instructions, upon execution, cause the IHS to maintain the modification until the recovery image is loaded.

9 . A method, comprising:

performing, via an Information Handling System (IHS), a data download operation in a preboot environment, wherein the preboot environment comprises a Basic Input/Output System (BIOS) application; and

modifying, via the IHS, a frequency or speed of a processor of the IHS based, at least in part, upon an amount of downloaded data;

wherein modifying the frequency or speed comprises sending, via the BIOS application, a command to an Embedded Controller (EC) coupled to the processor, and wherein the command instructs the EC to set the processor to a higher power level; and

wherein modifying the frequency or speed comprises enforcing, via the BIOS application, a policy, and wherein the policy indicates a minimum amount of the downloaded data to trigger the modification.

10 . The method of claim 9 , wherein the downloaded data comprises a recovery image.

11 . The method of claim 10 further comprising maintaining, via the IHS, the modification until the recovery image is loaded.

12 . A hardware memory device having program instructions stored thereon that, upon execution by a processor of an Information Handling System (IHS), cause the IHS to:

perform a data download operation in a preboot environment, wherein the preboot environment comprises a Basic Input/Output System (BIOS) application; and

modify a frequency or speed of the processor based, at least in part, upon an amount of downloaded data;

wherein to modify the frequency or speed, the BIOS application is configured to send a command to an Embedded Controller (EC) coupled to the processor, and wherein the command instructs the EC to set the processor to a higher power level; and

wherein to modify the frequency or speed, the BIOS application is further configured to enforce a policy, and wherein the policy indicates a minimum amount of the downloaded data to trigger the modification.

13 . The hardware memory device of claim 12 , wherein the processor is part of a heterogenous computing platform selected from the group consisting of: a System-On-Chip (SoC), a Field-Programmable Gate Array (FPGA), and an Application-Specific Integrated Circuit (ASIC).

14 . The hardware memory device of claim 13 , wherein the heterogenous computing platform comprises a Reduced Instruction Set Computer (RISC) processor coupled to the EC via an interconnect, and wherein the interconnect comprises at least one of: an Advanced Microcontroller Bus Architecture (AMBA) bus, a QuickPath Interconnect (QPI) bus, or a HyperTransport (HT) bus.