Memory disaggregation method, computing system implementing the method

1 . A memory disaggregation computing system comprising:

a host server and a memory device connected through a compute express link (CXL) network,

wherein a computing complex of the host server is connected to a memory resource of the memory device through a CXL packet transmitted through the CXL network, and executes an application program by using the memory resource,

wherein the host server is configured to:

collect information about a memory resource of the memory device,

map the memory resource to a physical memory space of the host server based on the information, and

transmit to the memory device a base address of the physical memory space to which the memory resource is mapped, and

wherein the memory device is configured to store the base address in which the memory resource of the memory device is mapped to the physical memory space of the host server.

2 . The memory disaggregation computing system of claim 1 , wherein the memory device includes:

the memory resource,

a memory controller of the memory resource, and

a CXL controller receiving a first CXL packet including a memory request of the host server, converting the first CXL packet into the memory request for the memory controller, and delivering the memory request, and converting a result processed by the memory controller into a second CXL packet, and transmitting the second CXL packet to the host server.

3 . The memory disaggregation computing system of claim 2 , wherein the memory request includes a data load command in the memory device or a data store command in the memory device.

4 . The memory disaggregation computing system of claim 1 , wherein the CXL packet is transmitted according to a CXL.mem protocol.

5 . The memory disaggregation computing system of claim 1 , wherein the information and the base address are transmitted according to a CXL.io protocol.

6 . The memory disaggregation computing system of claim 1 , further comprising:

at least one CXL switch connecting the host server and the memory device.

7 . A memory disaggregation computing system comprising:

a host server and a memory device connected through a compute express link (CXL) network including CXL switches,

wherein a computing complex of the host server is connected to a memory resource of the memory device through a first CXL packet transmitted through the CXL network, and executes an application program by using the memory resource,

wherein a first CXL switch is configured to:

configure a host identifier of at least one host server for each upstream port (USP),

upon receiving a second CXL packet whose destination port is connected to a second CXL switch, add a corresponding host identifier to the second CXL packet, and

transmit to the second CXL switch the second CXL packet to which the corresponding host identifier is added.

8 . A memory disaggregation computing system comprising:

a host server and a memory device connected through a compute express link (CXL) network including at least one CXL switch,

wherein a computing complex of the host server is connected to a memory resource of the memory device through a CXL packet transmitted through the CXL network, and executes an application program by using the memory resource,

wherein the CXL switch includes a computing complex configured to process a command from the host server, and

wherein the computing complex is configured to:

in response to the command, perform an operation on data stored in the memory resource on behalf of the host device by accessing the memory device, and

provide a result of the operation to the host server.

9 . The memory disaggregation computing system of claim 1 , wherein the memory resource includes a base address register (BAR) and a memory of the memory device managed by the host server.

10 . The memory disaggregation computing system of claim 9 , wherein the information includes a size of the BAR and a size of the memory.

11 . The memory disaggregation computing system of claim 7 , wherein the first CXL switch is further configured to:

upon receiving a third CXL packet whose destination port is connected to the host device or the memory device, remove the corresponding host identifier added to the third CXL packet, and

transmit the third packet in which the corresponding host identifier is removed to the host device or the memory device.