IHS (information handling system) mesh architecture for circuit optimization

1 . An Information Handling System (IHS) that comprises:

one or more central processors;

one or more first memory devices that comprise stored computer-readable instructions that, upon execution by the one or more central processors, cause a mesh control block program to:

determine availability of mesh resources that comprise resources of a first removeable processor;

reserve available mesh resources that comprise a plurality of available processor cores of the first removeable processor;

assign a plurality of portions of a circuit optimization to be executed in parallel by a respective plurality of reserved processor cores of the first removeable processor;

collect results determined by the first removeable processor based at least in part on parallel execution of the plurality of portions of the circuit optimization;

collect a log that indicates utilization levels of reserved mesh resources of the first removeable processor in determination of the results; and

evaluate the log to determine updates to the mesh resources that are available to be reserved for further use in the circuit optimization; and

at least one removeable processor that comprises:

a plurality of processor cores; and

one or more second memory devices that comprise stored computer-readable instructions that, upon execution by reserved processor cores of the plurality of processor cores, cause a mesh client program to:

determine the results at least in part by parallel execution of the plurality of portions of the circuit optimization assigned to the respective plurality of reserved processor cores by the mesh control block program;

track use of removeable processor resources while the results are determined; and

transmit, to the mesh control block program, the results and the log.

2 . The IHS of claim 1 , where execution of the instructions by the one or more central processors further causes the mesh control block program to generate a manifest that specifies the available mesh resources of the first removeable processor to be reserved for use in the circuit optimization.

3 . The IHS of claim 2 , where execution of the instructions by the one or more central processors further causes the mesh control block program to transmit to the first removeable processor, the manifest that specifies the mesh resources of the first removeable processor to be reserved for use in the circuit optimization.

4 . The IHS of claim 3 , where execution of the instructions by the reserved processor cores of the plurality of processor cores further causes the mesh client program to allocate the mesh resources of the first removeable processor specified in the manifest for exclusive use by the mesh client program.

5 . The IHS of claim 1 , wherein the at least one removeable processor further comprises at least one of a Graphics Processing Unit (GPU) or a Data Processing Unit (DPU).

6 . The IHS of claim 1 , where execution of the instructions by the reserved processor cores of the plurality of processor cores further causes the mesh client program to update the availability of the mesh resources of the first removeable processor that are available for assignment by the mesh control block program.

7 . The IHS of claim 1 , wherein the circuit optimization comprises a plurality of impedance calculations.

8 . The IHS of claim 7 , wherein the plurality of portions of the circuit optimization assigned to the first removeable processor comprise one or more of the plurality of impedance calculations for a first set of frequencies.

9 . The IHS of claim 8 , wherein the plurality of portions of the circuit optimization assigned to a second removeable processor comprise calculation of one or more of the plurality of impedance calculations for a second set of frequencies.

10 . The IHS of claim 9 , wherein assignment of the calculation of impedance calculations at the second set of frequencies increases fidelity of the circuit optimization.

11 . The IHS of claim 1 , wherein the IHS further comprises a remote access controller configured to collect information that indicates the availability of the mesh resources.

12 . The IHS of claim 11 , wherein information that indicates the availability of the mesh resources is collected at least in part via a sideband management connection between the remote access controller and the mesh resources.

13 . A method comprising:

determining, by a mesh control block operated by a central processor of an Information Handling System (IHS), availability of one or more mesh resources, wherein available mesh resources comprise a plurality of processor cores of a first removeable processor;

reserving, by the mesh control block, available mesh resources of the first removeable processor for use in a circuit optimization;

assigning, by the mesh control block, a plurality of portions of the circuit optimization to be executed in parallel by the first removeable processor using a respective plurality of reserved processor cores;

determining, by a mesh client operated by the first removeable processor, results of the circuit optimization, at least in part by executing the plurality of portions of the circuit optimization in parallel using the respective plurality of reserved processor cores;

tracking, by the mesh client, use of mesh resources of the first removeable processor during the determination of the results;

collecting, by the mesh control block, a log indicating utilization levels of the reserved mesh resources of the first removeable processor used in determining the results;

transmitting, by the mesh client to the mesh control block, the results and the log; and

evaluating, by the mesh control block, the log to determine updates to the mesh resources that are available to be reserved for further use in the circuit optimization.

14 . The method of claim 13 , wherein the method further comprises determining available mesh resources of a plurality of removeable processors that each comprise at least one of a Graphics Processing Unit (GPU) or a Data Processing Unit (DPU).

15 . The method of claim 13 , further comprising updating, by the mesh client, the availability of the mesh resources of the first removeable processor that are available for assignment by the mesh control block.

16 . The method of claim 13 , wherein the circuit optimization further comprises a plurality of impedance calculations.

17 . The method of claim 16 , wherein the plurality of portions of the circuit optimization assigned to the first removeable processor further comprise one or more of the plurality of impedance calculations for a first set of frequencies.

18 . A system that comprises:

one or more central processors coupled to one or more first memory devices that comprise stored computer-readable instructions that, upon execution by the one or more central processors, cause a mesh control block program to:

determine availability of one or more mesh resources, wherein available mesh resources comprise a plurality of processor cores of a first removeable processor of a plurality of removeable processors;

reserve available mesh resources of the first removeable processor for use in a circuit optimization;

assign a plurality of portions of the circuit optimization to be executed in parallel by the first removeable processor on a respective plurality of reserved processor cores;

determine results based at least in part upon parallel execution of the assigned plurality of portions of the circuit optimization by the respective plurality of reserved processor cores of the first removable processor;

collect a log that indicates utilization levels of the reserved mesh resources in determination of the results; and

evaluate the log to determine updates to the mesh resources that are available to be reserved for further use in the circuit optimization; and

the plurality of removeable processors, each comprising a plurality of processor cores and one or more second memory devices that comprise stored computer-readable instructions that, upon execution by the plurality of reserved processor cores, cause a mesh client program to:

determine the results by parallel execution of the plurality of portions of the circuit optimization by the respective plurality of reserved processor cores;

track use of reserved mesh resources of the first removeable processor in determination of the results; and

transmit, to the mesh control block, the results and the log.

19 . The system of claim 18 , wherein at least one of the plurality of removeable processors further comprise at least one of a Graphics Processing Unit (GPU) or a Data Processing Unit (DPU).

20 . The system of claim 18 , wherein the circuit optimization further comprises a plurality of impedance calculations.