Lock and buffer scheduling in multi-core architectures
Application code is compiled to generate code to be executed by the cores of a multi-core architecture. Generating the code includes mapping kernels of the application onto the DPEs, and generating main code for cores of the DPEs. The main code is generated by initializing locks for each kernel associated with the cores the DPEs. The locks are associated with input ports and output ports of the kernels. Further, buffers are initialized for the kernels. The buffers are associated with the locks and data streams. Subsequent to initializing the locks and initializing the buffers, the kernels are executed to generate data samples from the data streams. Subsequent to executing the kernels, the locks are released for subsequent calls of the kernels.
1 . A method comprising:
mapping, based on graph representation of an application, kernels of the application onto data processing engines (DPEs) of a DPE array;
generating main code for cores of the DPEs, wherein generating the main code includes:
initializing locks for each kernel associated with the cores the DPEs, each of the locks is associated with a respective input port or output port of a respective one of the kernels;
initializing buffers for the kernels, each of the buffers is associated with a respective lock of the locks and a data stream of data streams;
executing, subsequent to initializing the locks and initializing the buffers, the kernels to generate data samples from the data streams;
releasing, subsequent to executing the kernels, the locks associated with the kernels for subsequent calls of the kernels for the cores;
adjusting, subsequent to executing the kernels and releasing the locks, the buffers to point one or more of the buffers to an unused memory bank of a memory; and
implementing one or more of the kernels in each of the cores of the DPEs; and
generating control code to configure direct memory access (DMA) and switch circuitry in the DPE array based on data associated with each of the kernels.
2 . The method of claim 1 , wherein the buffers include ping buffers and pong buffers, and wherein adjusting the buffers further includes adjusting between the ping buffers and the pong buffers in a subsequent iteration.
3 . The method of claim 2 further comprising copying data between the ping buffers and the pong buffers.
4 . The method of claim 1 further comprising simulating the kernels to generate samples from the data streams.
5 . The method of claim 1 , wherein each input port of each of the kernels is associated with a respective buffer of the buffers and each output port of each of the kernels is associated with a respective buffer of the buffers.
6 . The method of claim 1 , wherein each of the buffers is associated with two respective memory banks of the memory, and adjusting the buffers to point the one or more of the buffers to the unused memory bank of a memory comprises adjusting a first buffer of the buffers to point from a first memory bank during a first iteration to a second memory bank during a second iteration.
7 . A non-transitory computer readable medium having stored thereon instructions that when executed by a processor cause the processor to:
map, based on a graph representation of an application, kernels of the application onto cores of data processing engines (DPEs) of a DPE array; and
generate main code for the cores of the DPEs, wherein generating the main code includes:
initializing locks for the kernels, each of the locks is associated with a respective input port or output port of a respective kernel of the kernels;
initializing buffers for the kernels, each of the buffers is associated with a respective lock of the locks and a data stream of data streams;
executing, subsequent to initializing the locks and initializing the buffers, one or more of the kernels having an external input to generate data samples from the data streams;
releasing, subsequent to executing the kernels, the locks associated with the kernels;
adjusting, subsequent to executing the kernels and releasing the locks, the buffers to point one or more of the buffers to an unused memory bank of a memory; and
implementing the one or more of the kernels in each of the cores of the DPEs;
generating control code to configure direct memory access (DMA) and switch circuitry in the DPE array based on data associated with each of the kernels.
8 . The non-transitory computer readable medium of claim 7 , wherein the buffers include ping buffers and pong buffers, and wherein adjusting the buffers includes adjusting between the ping buffers and the pong buffers in a subsequent iteration.
9 . The non-transitory computer readable medium of claim 8 , wherein the processor is further caused to copy data between the ping buffers and the pong buffers.
10 . The non-transitory computer readable medium of claim 7 , wherein the processor is further caused to simulate the kernels to generate samples from the data streams.
11 . The non-transitory computer readable medium of claim 7 , wherein each input port of each of the kernels is associated with a respective buffer of the buffers and each output port of each of the kernels is associated with a respective buffer of the buffers.
12 . The non-transitory computer readable medium of claim 7 , wherein each of the buffers is associated with two respective memory banks of the memory, and adjusting the buffers to point the one or more of the buffers to the unused memory bank of a memory comprises adjusting a first buffer of the buffers to point from a first memory bank during a first iteration to a second memory bank during a second iteration.
13 . A computer system comprising:
a memory configured to store program code; and
a processor configured to execute the program code to:
map, based on a graph representation of an application, kernels of the application onto data processing engines (DPEs) of a DPE array; and
generate main code for cores of the DPEs, wherein generating the main code includes:
initializing locks for each of the kernels associated with the cores the DPEs, each of the locks is associated with a respective input port or output port of a respective one of the kernels;
initializing buffers for the kernels, each of the buffers is associated with a respective lock of the locks and a data stream of data streams;
executing, subsequent to initializing the locks and initializing the buffers, the kernels to generate data samples from the data streams;
releasing, subsequent to executing the kernels, the locks associated with the kernels;
adjusting, subsequent to executing the kernels and releasing the locks, the buffers to point one or more of the buffers to an unused memory bank of a memory;
implementing one or more of the kernels in each of the cores of the DPEs; and
generating control code to configure direct memory access (DMA) and switch circuitry in the DPE array based on data associated with each of the kernels.
14 . The computer system of claim 13 , wherein the buffers include ping buffers and pong buffers, and wherein adjusting the buffers includes adjusting between the ping buffers and the pong buffers in a subsequent iteration.
15 . The computer system of claim 14 , wherein the processor is further configured to copy data between the ping buffers and the pong buffers.
16 . The computer system of claim 13 , wherein the processor is further configured to simulate the kernels to generate samples from the data streams.
17 . The computer system of claim 13 , wherein each input port of each of the kernels is associated with a respective buffer of the buffers and each output port of each of the kernels is associated with a respective buffer of the buffers.
18 . The computer system of claim 13 , wherein each of the buffers is associated with two respective memory banks of the memory, and adjusting the buffers to point the one or more of the buffers to the unused memory bank of a memory comprises adjusting a first buffer of the buffers to point from a first memory bank during a first iteration to a second memory bank during a second iteration.