IP Library Granted Patent US 12681791
Granted Patent B2
US 12681791 · App. 18/935,864 · Granted Jul 14, 2026

BMC/BIOS RAS system

Inventors: Wei Liu (Austin, TX); Ching-Lung Chao (Austin, TX)
Assignee: Dell Products L.P.
G06F11/0772G06F11/0778G06F11/079
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Quick Facts
Patent No.
US 12681791
App. No.
18/935,864
Granted
Jul 14, 2026
Kind
B2
Abstract

A BMC/BIOS RAS system includes a computing device including a processing system coupled to a BMC device and a computing component. A host processing device in the processing system identifies that the computing component has reached a first error threshold and, in response, notifies the BMC device. In response to being notified, the BMC device identifies and stores error telemetry data associated with at least one error that occurred in the computing component. One of the host processing device or the BMC device identifies that the computing component has reached a second error threshold and, in response, notifies a BIOS included in the processing system. In response to being notified the BIOS identifies and logs that the computing component has reached the second error threshold.

Claims (53)

1 . A Baseboard Management Controller (BMC)/Basic Input/Output System (BIOS) Reliability, Availability, and Serviceability (RAS) system, comprising:

a computing device;

a computing component included in the computing device;

a Baseboard Management Controller (BMC) device included in the computing device; and

a processing system that is included in the computing device and coupled to the computing component and the BMC device, wherein the processing system includes a host processing device that is configured to:

identify that the computing component has reached a first error threshold; and

notify, in response to identifying that the computing component has reached the first error threshold, the BMC device, wherein the BMC device is configured to:

identify and store, in response to being notified, error telemetry data associated with at least one error that occurred in the computing component, and wherein one of the host processing device or the BMC device is configured to:

identify that the computing component has reached a second error threshold; and

notify, in response to identifying that the computing component has reached the second error threshold, a Basic Input/Output System (BIOS) that is included in the processing system, wherein the BIOS is configured to:

 identify and log, in response to being notified, that the computing component has reached the second error threshold.

2 . The system of claim 1 , wherein the first error threshold is different than the second error threshold.

3 . The system of claim 2 , wherein the first error threshold is one error, and wherein the second error threshold is a plurality of errors.

4 . The system of claim 1 , wherein the computing component is a memory device.

5 . The system of claim 1 , wherein the BIOS is configured to:

transmit, in response to being notified, an error warning message to the host processing device, and wherein the host processing device is configured to:

perform, in response to receiving the error warning message, an error threshold action.

6 . The system of claim 1 , wherein the error telemetry data identifies a location of the at least one error that occurred in the computing component.

7 . An Information Handling System (IHS), comprising:

a processing system including a host processing device and a Basic Input/Output System (BIOS); and

a memory system that is coupled to the processing system and that includes instructions that, when executed by the host processing device, cause the host processing device to provide a host processing engine that is configured to:

identify that a computing component that is coupled to the processing system has reached a first error threshold;

notify, in response to identifying that the computing component has reached the first error threshold, a Baseboard Management Controller (BMC) device that is coupled to the processing system to cause the BMC device to identify and store error telemetry data associated with at least one error that occurred in the computing component;

identify that the computing component has reached a second error threshold; and

notify, in response to identifying that the computing component has reached the second error threshold, the BIOS, wherein memory system includes instructions that, when executed by the BIOS, cause the BIOS to provide a BIOS engine that is configured to:

identify and log, in response to being notified, that the computing component has reached the second error threshold.

8 . The IHS of claim 7 , wherein the first error threshold is different than the second error threshold.

9 . The IHS of claim 8 , wherein the first error threshold is one error, and wherein the second error threshold is a plurality of errors.

10 . The IHS of claim 7 , wherein the computing component is a memory device.

11 . The IHS of claim 7 , wherein the BIOS engine is configured to:

transmit, in response to being notified, an error warning message to the host processing engine, and wherein the host processing engine is configured to:

perform, in response to receiving the error warning message, an error threshold action.

12 . The IHS of claim 11 , wherein the error threshold action includes at least one of:

configuring a backup component for the computing component; and

preventing, via an operating system provided by the host processing device, access to at least a portion of the computing component that is associated with the error.

13 . The IHS of claim 7 , wherein the error telemetry data identifies a location of the at least one error that occurred in the computing component.

14 . A method for performing Reliability, Availability, and Serviceability (RAS) operations using a Baseboard Management Controller (BMC) and a Basic Input/Output System (BIOS) in a computing device, comprising:

identifying, by a host processing device in a processing system, that a computing component that is coupled to the processing system has reached a first error threshold;

notifying, by the host processing device in response to identifying that the computing component has reached the first error threshold, a Baseboard Management Controller (BMC) device that is coupled to the processing system;

identifying and storing, by the BMC device, error telemetry data associated with at least one error that occurred in the computing component;

identifying, by the one of the host processing device or the BMC device, that the computing component has reached a second error threshold;

notifying, by one of the host processing device or the BMC device in response to identifying that the computing component has reached the second error threshold, the BIOS; and

identifying and logging, by the BIOS in response to being notified, that the computing component has reached the second error threshold.

15 . The method of claim 14 , wherein the first error threshold is different than the second error threshold.

16 . The method of claim 15 , wherein the first error threshold is one error, and wherein the second error threshold is a plurality of errors.

17 . The method of claim 14 , wherein the computing component is a memory device.

18 . The method of claim 14 , further comprising:

transmitting, by the BIOS in response to being notified, an error warning message to the host processing device; and

performing, by the host processing device in response to receiving the error warning message, an error threshold action.

19 . The method of claim 14 , wherein the error threshold action includes at least one of:

configuring a backup component for the computing component; and

preventing, via an operating system provided by the host processing device, access to at least a portion of the computing component that is associated with the error.

20 . The method of claim 14 , wherein the error telemetry data identifies a location of the at least one error that occurred in the computing component.