IP Library › Granted Patent US 12681801
Granted Patent B2
US 12681801 · App. 18/584,508 · Granted Jul 14, 2026

Memory system

Inventors: Yuko Noda (Kawasaki Kanagawa, JP); Kiwamu Watanabe (Kawasaki Kanagawa, JP); Masahiro Saito (Tokyo, JP); Yoshiki Takai (Fujisawa Kanagawa, JP)
Assignee: Kioxia Corporation
G06F11/1016G06F11/076G06F11/1068
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12681801
App. No.
18/584,508
Granted
Jul 14, 2026
Kind
B2
Abstract

A memory system includes a nonvolatile memory including a memory cell, and a controller. The controller is configured to write multi-bit data into the memory cell through a first write operation of writing a first part, and not a second part, of the multi-bit data and then a second write operation of writing the first and second parts. The controller is configured to, during writing of the multi-bit data, determine an amount of time that has passed since the first write operation, perform the second write operation in a first manner by inputting the second part, and not the first part, from the controller, when the determined amount is less than a threshold amount, and perform the second write operation in a second manner by inputting the first and second parts from the controller, when the determined amount is greater than the threshold amount.

Claims (68)

1 . A memory system comprising:

a nonvolatile memory including a memory cell transistor; and

a controller configured to write multi-bit data into the memory cell transistor through a first write operation of writing a first part of the multi-bit data and not a second part of the multi-bit data to the memory cell transistor, and then a second write operation of writing the first and second parts of the multi-bit data to the memory cell transistor after the first write operation, wherein

the controller is configured to, during writing of the multi-bit data,

determine an amount of time that has passed since the first write operation to the memory cell transistor;

determine whether or not the determined amount of time is less than a threshold amount or greater than the threshold amount, comparing the determined amount of time with the threshold amount;

perform the second write operation to the memory cell transistor in a first manner when it is determined that the determined amount of time is less than the threshold amount; and

perform the second write operation to the memory cell transistor in a second manner when it is determined that the determined amount of time is greater than the threshold amount,

in the second write operation in the first manner, the controller inputs the second part of the multi-bit data, and not the first part, into the nonvolatile memory, and causes the nonvolatile memory to read the first part of the multi-bit data from the memory cell transistor and write the read first part of the multi-bit data and the input second part of the multi-bit data into the memory cell transistor, and

in the second write operation in the second manner, the controller inputs the first and second parts of the multi-bit data into the nonvolatile memory, and causes the nonvolatile memory to write the input first and second parts of the multi-bit data into the memory cell transistor.

2 . The memory system according to claim 1 , further comprising:

a volatile memory,

the controller is configured to store the multi-bit data in the volatile memory when performing the writing of the multi-bit data, and

when the controller performs the second write operation in the second manner, the controller reads the first part of the multi-bit data from the volatile memory and inputs the first part of the multi-bit data read from the volatile memory into the nonvolatile memory.

3 . The memory system according to claim 1 , wherein when the controller performs the second write operation in the second manner, the controller receives the first part of the multi-bit data read from the memory cell transistor and inputs bit data obtained from the received first part of the multi-bit data into the nonvolatile memory.

4 . The memory system according to claim 3 , wherein the controller is further configured to perform data detection and correction with respect to the received first part of the multi-bit data to obtain the bit data.

5 . The memory system according to claim 1 , wherein the first part of the multi-bit data is two or more bits and the second part of the multi-bit data is two or more bits.

6 . A memory system comprising:

a nonvolatile memory including a memory cell transistor; and

a controller configured to write multi-bit data into the memory cell transistor through a first write operation of writing a first part of the multi-bit data and not a second part of the multi-bit data to the memory cell transistor, and then a second write operation of writing the first and second parts of the multi-bit data to the memory cell transistor after the first write operation, wherein

the controller is configured to, during writing of the multi-bit data,

determine a number of error bits included in the first part of the multi bit data written through the first write operation into the memory cell transistor and read therefrom;

determine whether the determined number of error bits is greater than a threshold number or less than the threshold number, comparing the determined number of error bits with the threshold number;

perform the second write operation to the memory cell transistor in a first manner, when it is determined that the determined number of error bits is less than the threshold number; and

perform the second write operation to the memory cell transistor in a second manner, when it is determined that the determined number of error bits is greater than the threshold number,

in the second write operation in the first manner, the controller inputs the second part of the multi-bit data, and not the first part, into the nonvolatile memory, and causes the nonvolatile memory to read the first part of the multi-bit data from the memory cell transistor and write the read first part of the multi-bit data and the input second part of the multi-bit data into the memory cell transistor, and

in the second write operation in the second manner, the controller inputs the first and second parts of the multi-bit data into the nonvolatile memory, and causes the nonvolatile memory to write the input first and second parts of the multi-bit data into the memory cell transistor.

7 . The memory system according to claim 6 , further comprising:

a volatile memory,

the controller is configured to store the multi-bit data in the volatile memory when performing the writing of the multi-bit data, and

when the controller performs the second write operation in the second manner, the controller reads the first part of the multi-bit data from the volatile memory and inputs the first part of the multi-bit data read from the volatile memory into the nonvolatile memory.

8 . The memory system according to claim 7 , wherein when the controller performs the second write operation in the second manner, the controller receives the first part of the multi-bit data read from the memory cell transistor and inputs bit data obtained from the received first part of the multi-bit data into the nonvolatile memory.

9 . The memory system according to claim 8 , wherein the controller is further configured to perform data detection and correction with respect to the received first part of the multi-bit data to obtain the bit data.

10 . The memory system according to claim 6 , wherein the controller is further configured to control the nonvolatile memory to transmit the first part of the multi-bit data in the memory cell transistor to the controller when the second write operation has not been performed during a predetermined period of time from the first write operation.

11 . The memory system according to claim 10 , wherein the controller is further configured to perform data detection and correction with respect to the first part of the multi-bit data transmitted from the nonvolatile memory.

12 . The memory system according to claim 6 , wherein the first part of the multi-bit data is two or more bits and the second part of the multi-bit data is two or more bits.

13 . A memory system comprising:

a nonvolatile memory including a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor; and

a controller configured to:

write multi-bit data into the first memory cell transistor through a first write operation of writing a first part of the multi-bit data and not a second part of the multi-bit data to the first memory cell transistor, and then a second write operation of writing the first and second parts of the multi-bit data to the first memory cell transistor after the first write operation; and

perform a third write operation of writing first one or more bits of the first part into the second memory cell transistor and second one or more bits of the first part into the third memory cell transistor,

wherein the controller is configured to, during the writing of the multi-bit data into the first memory cell transistor, perform the second write operation in a first manner, in which the controller:

causes the nonvolatile memory to read the first one or more bits and the second one or more bits of the first part from the second and third memory cell transistors, respectively,

inputs the second part of the multi-bit data from the controller into the nonvolatile memory; and

causes the nonvolatile memory to write the first part of the multi-bit data including the first one or more bits and the second one or more bits read from the second and third memory transistors and the input second part of the multi-bit data into the first memory cell transistor.

14 . The memory system according to claim 13 , wherein the controller performs the third write operation during the writing of the multi-bit data before the first write operation.

15 . The memory system according to claim 13 , wherein the controller is configured to:

determine an amount of time that has passed since the first write operation; and

perform the third write operation when the determined amount of time is greater than a threshold amount.

16 . The memory system according to claim 15 , wherein the controller is configured to, during writing of the multi-bit data into the first memory cell transistor:

perform the second write operation in the first manner, when the determined amount of time is greater than the threshold amount; and

perform the second write operation in a second manner, when the determined amount of time is less than the threshold amount,

wherein in the second write operation in the second manner, the controller:

causes the nonvolatile memory to read the first part of the multi-bit data from the first memory cell transistor;

inputs the second part of the multi-bit data from the controller into the nonvolatile memory; and

causes the nonvolatile memory to write the first part of the multi-bit data read from the first memory cell transistor and the input second part of the multi-bit data into the first memory cell transistor.

17 . The memory system according to claim 13 , wherein the controller is configured to:

determine a number of error bits included in the first part of the multi bit data written into the first memory cell transistor through the first write operation and read therefrom; and

perform the third write operation when the number of error bits is greater than a threshold number.

18 . The memory system according to claim 15 , wherein the controller is configured to, during writing of the multi-bit data into the first memory cell transistor:

perform the second write operation in the first manner, when the number of error bits is greater than the threshold number; and

perform the second write operation in a second manner, when the number of error bits is less than the threshold number,

wherein in the second write operation in the second manner, the controller:

causes the nonvolatile memory to read the first part of the multi-bit data from the first memory cell transistor;

inputs the second part of the multi-bit data from the controller into the nonvolatile memory; and

causes the nonvolatile memory to write the first part of the multi-bit data read from the first memory cell transistor and the input second part of the multi-bit data into the first memory cell transistor.

19 . The memory system according to claim 13 , wherein the controller is further configured to control the nonvolatile memory to transmit the first part of the multi-bit data in the first memory cell transistor to the controller when the second write operation has not been performed during a predetermined period of time from the first write operation.

20 . The memory system according to claim 19 , wherein the controller is further configured to perform data detection and correction with respect to the first part of the multi-bit data transmitted from the nonvolatile memory.