Deep neural network implementation for soft decoding of BCH code

1 . A memory system comprising:

a memory device; and

a controller configured to output a decoded codeword from the memory device in connection with a read operation performed on the memory device, the controller including:

a soft information generator configured to generate log-likelihood ratios (LLRs) and a syndrome vector corresponding to bits of a received codeword from the memory device; and

a neural network configured to obtain a set of confidence values based on the LLRs and the syndrome vector, wherein each of the set of confidence values corresponds to a respective bit of the received codeword,

wherein the set of confidence values is used to determine the decoded codeword by guiding error correction on the bits of the received codeword.

2 . The memory system of claim 1 , wherein the controller further includes a solver configured to:

estimate an error vector based on selecting one or more bit locations with confidence values from the set of confidence values above threshold value; and

calculate a sum LLR score for the estimated error vector,

wherein the decoded codeword is determined based on the estimated error vector and the sum LLR score.

3 . The memory system of claim 1 , wherein the soft information generator is configured to:

generate the LLRs by performing soft sampling based on issuing multiple page-reads on a channel, wherein the channel is an additive noise channel; and

determine the syndrome vector for the codeword based on a parity check matrix and a hard decision vector of a channel output of the channel.

4 . The memory system of claim 3 , wherein the syndrome vector corresponds to a difference between an expected parity check value and an actual parity check value, and wherein each value per bit of the LLR values is a scaled version of the channel output of the channel, and wherein the decoded codeword comprises a sum of reliabilities of all error locations.

5 . The memory system of claim 1 , wherein the neural network comprises a trained model, wherein the trained model is a fully-connected (FC) deep neural network (DNN) comprising rectified linear unit (ReLU) activation nodes.

6 . The memory system of claim 1 , wherein the neural network is configured to execute a softmax function to obtain the set of confidence values for each bit of the received codeword.

7 . The memory system of claim 1 , wherein the controller is configured to output the decoded codeword by performing soft BCH decoding and wherein the codeword is BCH component code.

8 . The memory system of claim 1 , wherein the neural network is configured to correct multiple errors.

9 . The memory system of claim 3 , wherein the neural network is trained on noisy codewords generated by the channel.

10 . The memory system of claim 1 , wherein the codeword comprises a plurality of component codes, and wherein the neural network is included in each of a plurality of component code decoders corresponding to the plurality of component codes.

11 . A memory system comprising:

a memory device; and

a controller configured to output a decoded codeword from the memory device in connection with a read operation performed on the memory device, the controller including:

a soft information generator configured to generate log-likelihood ratios (LLRs) and a syndrome vector corresponding to bits from the memory device; and

an iterative solver including a neural network, wherein the iterative solver is configured to:

obtain, during a first iteration of a plurality of iterations, a set of confidence values based on the LLRs and the syndrome vector, wherein each of the set of confidence values corresponds to a respective bit of the received codeword,

estimate, during the first iteration, an error vector based on selecting one or more bit locations with respective confidence values above a threshold value;

identify, during the first iteration, a first bit location from the error vector with a first highest confidence value; and

update, during the first iteration, the syndrome vector corresponding to a bit-flip at the first bit location.

12 . The memory system of claim 11 , wherein the iterative solver is further configured to:

update, during the first iteration, a bit of a first LLR at the first bit location;

update, during the first iteration, a sum LLR score based on a first LLR score of the first LLR; and

determine the decoded codeword based on the estimated error vector and the sum LLR score, responsive to completing the plurality of iterations.

13 . The memory system of claim 11 , wherein the soft information generator is configured to:

generate the LLRs by performing soft sampling based on issuing multiple page-reads on a channel, wherein the channel is an additive noise channel; and

determine the syndrome vector for the received codeword based on a parity check matrix and a hard decision vector of a channel output of the channel.

14 . The memory system of claim 11 , wherein the neural network comprises a trained model, wherein the trained model is a fully-connected (FC) deep neural network (DNN) comprising rectified linear unit (ReLU) activation nodes.

15 . The memory system of claim 11 , wherein the neural network is configured to execute a softmax function to obtain the set of confidence values for each bit of the received codeword.

16 . The memory system of claim 13 , wherein the neural network is trained on noisy codewords generated by the channel.

17 . A computer-implemented method comprising:

obtaining a log-likelihood ratios (LLRs) and a syndrome vector from bits of a codeword received from a memory device in connection with a read operation performed on the memory device;

using a neural network to obtain a set of confidence values based on the LLRs and the syndrome vector, wherein each of the set of confidence values corresponds to a respective bit of the received codeword; and

determining a decoded codeword based on the set of confidence values by guiding error correction on the bits of the received codeword.

18 . The computer-implemented method of claim 17 , further comprising:

determining the syndrome vector for the received bits based on a parity check matrix and a hard decision vector of a channel output of the channel, wherein the syndrome vector is further determined based on the hard decision vector being multiplied by the parity check matrix.

19 . The computer-implemented method of claim 18 , wherein the syndrome vector corresponds to a difference between an expected parity check value and an actual parity check value, and wherein each value per bit of the set of LLR values is a scaled version of a channel output of the channel, and wherein the decoded codeword comprises a sum of reliabilities of all error locations, and wherein the hard decision vector comprises binary values for each bit of the codeword, and wherein the parity check matrix is an m by n (m×n) matrix where m is a number of check equations and n is a length of the codeword.

20 . The computer-implemented method of claim 17 , further comprising:

generating a plurality of candidate locations based on reliabilities of each bit of the received codeword of a sorted set of LLRs of the set of the LLRs, wherein generating the plurality of candidate locations comprises independently analyzing each LLR of the sorted set of LLRs;

choosing a first subset of candidate locations of the plurality of candidate locations within a first span of the sorted set of LLRs, wherein the chosen first subset of candidate locations corresponds to a plurality of first lowest LLRs of the sorted set of LLRs, and wherein each candidate location of the first subset of candidate locations is a bit-flip candidate; and updating the syndrome vector based on the chosen first subset of candidate locations, and wherein the syndrome vector is associated with a candidate counter, and wherein for each candidate location of the first subset of candidate locations of the syndrome vector a counter is incremented by one.