Data processing

1 . Data processing apparatus comprising:

circuitry implementing a hardware processing module configured to initiate data handling transactions, for transmission to a hardware data handling module via a transaction interface, in response to successive processing instructions; and

a hardware verification module insertable as a subsystem into a circuitry design of the circuitry and connectable to the transaction interface and configured to detect, at the transaction interface, test data, representing an ordered series of communications from the hardware processing module to the hardware data handling module and from the hardware data handling module to the hardware processing module via the transaction interface generated in response to a test series of the processing instructions;

wherein the test data comprises memory access properties comprising an order and a number of the communications;

wherein the hardware verification module is configured to capture the memory access properties at the transaction interface; and

wherein the hardware verification module is configured to compare two or more instances of the test data, to detect whether the two or more instances of the test data are identical, and to signal, in case that the two or more instances of the test data are identical, a pass outcome in the circuitry or, in case that the two or more instances of the test data are not identical, a fail outcome in the circuitry.

2 . The apparatus according to claim 1 , wherein the hardware processing module is configured to execute the test series of the processing instructions two or more successive times, and the hardware verification module is configured to detect a respective instance of the test data corresponding to each time the test series of the processing instructions is executed.

3 . The apparatus according to claim 2 , in which the hardware processing module comprises a set of two or more processors configured to initiate data handling transactions which access a memory address space common to the set of two or more processors.

4 . The apparatus according to claim 3 , in which the hardware processing module is configured to execute the test series of the processing instructions using a first subset of the set of two or more processors and then to execute the test series of the processing instructions using a second, different, subset of the set of two or more processors.

5 . The apparatus according to claim 4 , wherein the first and second subsets of the set of two or more processors have a common instruction set architecture.

6 . The apparatus according to claim 4 , wherein the first and second subsets of the set of two or more processors have different respective data handling throughputs and different respective power consumptions.

7 . The apparatus according to claim 2 , wherein the hardware processing module is configured to execute a barrier instruction between initiation of each data handling transaction, for one instance of execution of the test series of the processing instructions.

8 . The apparatus according to claim 1 , wherein the hardware verification module is connectable to two or more different transaction interfaces and is configured to detect a respective instance of the test data corresponding to each transaction interface of the two or more different transaction interfaces.

9 . The apparatus according to claim 8 , comprising a hardware interconnect module providing a data connection between the hardware processing module and the hardware data handling module.

10 . The apparatus according to claim 9 , wherein one of the two or more transaction interfaces is an interface between the hardware processing module and the hardware interconnect module, and another of the two or more transaction interfaces is an interface between the hardware interconnect module and the hardware data handling module.

11 . The apparatus according to claim 1 , wherein each data handling transaction has an associated transaction identifier, and the hardware verification module is configured to detect transaction identifiers as part of the test data.

12 . The apparatus according to claim 1 , wherein the hardware processing module is configured to execute processing instructions to control operation of the hardware verification module.

13 . The apparatus according to claim 12 , wherein the hardware processing module is configured to generate the test series of the processing instructions.

14 . The apparatus according to claim 12 , wherein the hardware processing module is configured to enable and disable the operation of the hardware verification module.

15 . An integrated circuit comprising circuitry to provide the data processing apparatus according to claim 1 .

16 . A non-transitory computer-readable storage medium, storing a computer program for controlling a host data processing apparatus to provide a simulation environment, the computer program comprising:

a hardware processing module implementable in circuitry configured to initiate data handling transactions, for transmission to a data handling module via a transaction interface, in response to successive processing instructions; and

a hardware verification module insertable as a subsystem into a circuitry design of the circuitry and connectable to the transaction interface and configured to detect, at the transaction interface, test data, representing an ordered series of communications from the hardware processing module to the hardware data handling module and from the hardware data handling module to the hardware processing module via the transaction interface generated in response to a test series of the processing instructions;

wherein the test data comprise memory access properties comprising an order and a number of the communications;

wherein the hardware verification module is configured to capture the memory access properties at the transaction interface; and

wherein the hardware verification module is configured to compare two or more instances of the test data to detect whether the two or more instances of the test data are identical and to signal, in case that the two or more instances of the test data are identical, a pass outcome in the circuitry or, in case that the two or more instances of the test data are not identical, a fail outcome in the circuitry.

17 . A system comprising:

an integrated circuit providing circuitry to implement a hardware processing module configured to initiate data handling transactions, for transmission to a data handling module via a hardware transaction interface, in response to successive processing instructions, and a hardware verification module insertable as a subsystem into a circuitry design of the circuitry and connectable to the hardware transaction interface and configured to detect, at the transaction interface, hardware test data representing an ordered series of communications from the hardware processing module to the hardware data handling module and from the hardware data handling module to the hardware processing module via the hardware transaction interface generated in response to a test series of processing instructions; and

a computer program for controlling a host data processing apparatus to provide a simulation environment comprising an emulated processing module configured to initiate data handling transactions, for transmission to an emulated data handling module via an emulated transaction interface, in response to successive processing instructions, and an emulated verification module insertable as a subsystem into a circuitry design of the circuitry and connectable to the emulated transaction interface and configured to detect emulation test data, representing an ordered series of communications between the emulated processing module and the emulated handling module via the emulated transaction interface generated in response to the test series of the processing instructions;

wherein the test data comprise memory access properties comprising an order and a number of the communications;

wherein one or both of the hardware verification module and the emulated verification module are configured to capture the memory access properties at the transaction interface; and

wherein one or both of the hardware verification module and the emulated verification module are configured to compare two or more instances of the test data, at least one instance of the two or more instances being hardware test data and at least one instance of the two or more instances being emulation test data, to detect whether the two or more instances of the test data are identical, and to signal, in case that the two or more instances of the test data are identical, a pass outcome in the circuitry or, in case that the two or more instances of the test data are not identical, a fail outcome in the circuitry.

18 . A hardware verification module insertable as a subsystem into a circuitry design of a circuitry for use in a data processing apparatus comprising the circuitry implementing a hardware processing module configured to initiate data handling transactions, for transmission to a data handling module via a transaction interface, in response to successive processing instructions;

wherein the hardware verification module is connectable to the transaction interface and configured to detect, at the transaction interface, test data representing an ordered series of communications from the hardware processing module to the hardware data handling module and from the hardware data handling module to the hardware processing module via the transaction interface generated in response to a test series of the processing instructions;

wherein the test data comprise memory access properties comprising an order and a number of the communications;

wherein the hardware verification module is configured to capture the memory access properties at the transaction interface; and

wherein the hardware verification module is configured to compare two or more instances of the test data, to detect whether the two or more instances of the test data are identical, and to signal, in case that the two or more instances of the test data are identical, a pass outcome in the circuitry or, in case that the two or more instances of the test data are not identical, a fail outcome in the circuitry.

19 . A data processing method comprising:

providing a hardware processing module implementable or implemented in a circuitry configured to initiate data handling transactions, for transmission to a hardware data handling module via a transaction interface, in response to successive processing instructions;

using a hardware verification module insertable as a subsystem into a circuitry design of the circuitry for:

detecting, at the transaction interface, test data, representing an ordered series of communications from the hardware processing module to the hardware data handling module and from the hardware data handling module to the hardware processing module via the transaction interface generated in response to a test series of the processing instructions, wherein the test data comprise memory access properties comprising an order and a number of the communications;

capturing the memory access properties at the transaction interface;

comparing two or more instances of the test data;

detecting whether the two or more instances of the test data are identical; and

signalling, in case that the two or more instances of the test data are identical, a pass outcome in the circuitry or, in case that the two or more instances of the test data are not identical, a fail outcome in the circuitry.