Near-memory protocol analyzer

1 . A memory device comprising:

one or more integrated circuit (IC) memory dies configured as a memory array; and

a memory controller to control access to the memory array, the memory controller configured to:

receive a memory request from a host device;

collect packet trace data from the memory request;

include the packet trace data in a log stored in a log region of the memory array;

disable one or both of writing write data in the memory request to the memory array and returning read data for the memory request when a data disable is active in the memory controller; and

return the log to the host device.

2 . The memory device of claim 1 , wherein the memory controller is configured to:

receive multiple memory requests from the host device;

compare the memory requests to one or more packet trace filters;

capture packet trace data from only a subset of the multiple memory requests having properties specified in the one or more packet trace filters and not capture packet trace data from memory requests not having the properties specified in the one or more packet trace filters; and

store the captured packet trace data in the log.

3 . The memory device of claim 2 , wherein the memory controller is configured to:

receive the one or more packet trace filters from the host device;

receive a configuration from the host device of a log region of the memory array for the log;

collect packet trace data according to the one or more packet trace filters and store the packet trace data in the log region.

4 . The memory device of claim 1 , wherein the memory controller is configured to:

receive an indication of one or more fields of the memory request to include in the packet trace data; and

collect data from the indicated one or more fields of the memory request and store the data in the log as the packet trace data.

5 . The memory device of claim 1 , wherein the memory controller is configured to:

receive a memory read request with an indication of data disable from the host device;

log packet trace data from the memory request in the log;

disable including read data in a response to the memory read request; and

include read metadata in the response to the memory read request.

6 . The memory device of claim 1 , wherein the memory controller includes a marker control register writable by the host device, and wherein the memory controller is configured to store a marker value in the log with the packet trace data according to the marker control register.

7 . The memory device of claim 1 , wherein the memory controller is configured to:

receive a configuration from the host device of a first log region of the memory array for the log and a second log region for the log;

storing the packet trace data in a first log region of the log and storing the packet trace data in a second log region of the log when the first log region is full; and

wherein the returning the log to the host device includes returning the first log region when the first log region is full.

8 . A method of operating a memory device, the method comprising:

receiving, by a memory controller of the memory device, a memory request from a host device and receiving an indication of data disable from the host device;

collecting packet trace data from the memory request;

including the packet trace data receiving an indication of data disable from the host device in a log stored in a memory array of the memory device;

disabling writing data and disabling returning read data for the memory request in response to the indication of data disable; and

returning the log to the host device.

9 . The method of claim 8 , including:

receiving multiple memory requests from the host device;

capturing packet trace data from only a subset of the multiple memory requests having properties specified in one or more packet trace filters; and

storing the captured packet trace data in the log.

10 . The method of claim 9 , including:

receiving the one or more packet trace filters from the host device;

receiving a log size and log start address from the host device specifying a log region of the memory; and

capturing the packet trace data for the subset of multiple memory requests according to the one or more packet trace filters and storing the packet trace data in the log region of the memory array.

11 . The method of claim 9 , including:

receiving multiple memory requests from the host device;

receiving one or more data logging field enables from the host device; and

wherein the capturing the packet trace data includes only logging enabled packet trace data from the multiple memory requests in the log.

12 . The method of claim 9 , including:

logging packet trace data from the memory request in the log for the memory read request;

and

returning read metadata to the host device in a response to the memory read request.

13 . The method of claim 8 , wherein the receiving the memory request from the host device includes:

receiving a marker with the memory request; and

storing the marker in the log with the packet trace data for the memory request.

14 . The method of claim 13 , wherein the receiving the marker includes the host device writing a marker value to a marker control register of the memory controller to insert the marker value in the log.

15 . The method of claim 8 ,

wherein the storing the packet trace data in the log includes storing the packet trace data in a first log region of the log and storing the packet trace data in a second log region of the log when the first log region is full; and

wherein the returning the log to the host device includes returning the first log region when the first log region is full.

16 . A computer system comprising:

at least one host device including a host processor;

a memory bus and a host input/output (I/O) channel; and

at least one memory device coupled to the at least one host device by the memory bus and host I/O channel, wherein the memory device includes:

one or more integrated circuit (IC) memory dies configured as a memory array; and

a memory controller to control access to the memory array, the memory controller configured to:

reserve a log in the memory array according to log configuration information received from the at least one host device via the host I/O channel;

receive memory requests from the at least one host device via the memory bus;

store packet trace data from the memory requests in the log;

disable one or both of writing write data in the memory request to the memory array and returning read data for the memory request when a data disable is active in the memory controller; and

return the packet trace data stored in the log to the host device.

17 . The computer system of claim 16 , wherein the log configuration information received from the host device includes:

a log memory start address and a log memory size;

one or more packet trace filters;

one or more data field enables; and

wherein the memory controller is configured to:

capture packet trace data from only a subset of the multiple memory requests having properties specified in the one or more packet trace filters, and only capture packet trace data enabled by the one or more data field enables; and

store the captured packet trace data in the log.

18 . The computer system of claim 16 , wherein the memory controller includes:

a log status register readable via the host I/O channel, and

wherein the memory controller is configured to set the log status register to a log full status the log is full packet trace data.