Architecture and method for a hybrid virtual-physical cache
A computing system comprising: a cache, comprising a virtual tag storage and a physical tag storage, where each cache line is identified for load operations by a virtual tag and for store operations by a physical tag; a cache access controller; a snoop access circuitry; and a miss controller; wherein, in response to receiving a load operation comprising a virtual address, the cache access controller: accesses the cache to perform the load operation comprising looking up a virtual tag computed using the virtual address; and upon failing to identify the virtual tag value in the virtual tag storage, provides the load operation to the miss controller; and wherein the miss controller in response to receiving the load operation from the access controller, initiates an aliasing snoop to the cache by the snoop access circuitry, the aliasing snoop comprising looking up a physical tag computed using a corresponding physical address.
1 . A computing system comprising:
a lower level (L1) cache associated with at least one first processing circuitry, configured to store a first plurality of cache lines and comprising a storage of virtual tags (L1 storage of virtual tags) and a storage of physical tags (L1 storage of physical tags), where each of the first plurality of cache lines is identified for load operations by a first virtual tag in the L1 storage of virtual tags and for store operations by a first physical tag in the L1 storage of physical tags;
a lower cache access controller circuitry (L1 access controller), configured to access the L1 cache by the at least one first processing circuitry;
a snoop access circuitry associated with the at least one first processing circuitry, configured to access the L1 cache by at least one second processing circuitry; and
a lower cache miss controller circuitry (L1 miss controller);
wherein the L1 access controller is further configured to, in response to receiving from the at least one first processing circuitry a load operation comprising a virtual memory address:
access the L1 cache (L1 access) to perform the load operation comprising looking up in the L1 storage of virtual tags a virtual tag value computed using the virtual memory address; and
upon failing to identify the virtual tag value in the L1 storage of virtual tags (L1 virtual miss), provide the load operation to the L1 miss controller; and
wherein the L1 miss controller is configured to, in response to receiving the load operation from the L1 access controller, initiate another access to the L1 cache by the snoop access circuitry (L1 aliasing snoop), the L1 aliasing snoop comprising looking up in the L1 storage of physical tags a physical tag value computed using a first physical memory address corresponding to the virtual memory address.
2 . The computing system of claim 1 , wherein the L1 access controller is further configured to provide the L1 miss controller with the virtual tag value and the physical tag value.
3 . The computing system of claim 1 , wherein the snoop access circuitry is further configured to, upon a successful look up of the physical tag value in the L1 storage of physical tags (L1 aliasing snoop success):
retrieve from the L1 cache a respective cache line identified by the physical tag value; and
provide data from the respective cache line to the L1 miss controller.
4 . The computing system of claim 3 , wherein the snoop access circuitry is further configured to invalidate the respective cache line in the L1 storage of virtual tags and in the L1 storage of physical tags.
5 . The computing system of claim 3 , wherein the L1 miss controller is further configured to:
store the data of the respective cache line in another cache line of the first plurality of cache lines of the L1 cache, where the other cache line is selected according to a cache management policy;
update the L1 storage of physical tags to identify the other cache line by the physical tag value; and
update the L1 storage of virtual tags to identify the other cache line by the virtual tag value computed using the virtual memory address of the load operation.
6 . The computing system of claim 5 , wherein the other cache line, selected according to the cache management policy, is the respective cache line.
7 . The computing system of claim 5 , wherein the system further comprises a buffer, for storing local data retrieved by accessing the L1 cache, before sending the local data to at least one other processing circuitry;
wherein providing the data from the respective cache line to the L1 miss controller comprises storing the data in the buffer;
wherein the snoop access circuitry is further configured to indicate to the L1 miss controller a failure to update the L1 cache;
wherein the L1 miss controller is further configured to issue a lower level cache update (L1 cache update) in response to the indication from the snoop access circuitry failing to update the L1 cache;
wherein storing the data of the respective cache line in the other cache line, updating the L1 storage of physical tags and updating the L1 storage of virtual tags is in response to the L1 cache update.
8 . The computing system of claim 1 , further comprising a higher level (L2) cache, configured to store a second plurality of cache lines and comprising another storage of physical tags (L2 storage of physical tags), where each of the second plurality of cache lines is identified for both load and store operations by another physical tag in the L2 storage of physical tags and where the L2 cache is a next level memory with relation to the L1 cache;
wherein the L1 miss controller is further configured to initiate an access to the L2 cache (L2 access) using the physical tag value, concurrently with the L1 aliasing snoop.
9 . The computing system of claim 1 , wherein an L1 aliasing snoop success comprises identifying the physical tag value in a location in the L1 storage of physical tags.
10 . The computing system of claim 9 , wherein the snoop access is further configured to, in response to the L1 aliasing snoop success, update the L1 storage of virtual tags to identify the respective cache line by the virtual tag value computed using the virtual memory address of the load operation.
11 . The computing system of claim 10 , wherein the first plurality of cache lines is organized in the L1 storage of virtual tags in a plurality of cache sets each cache set comprising a plurality of ways;
wherein identifying the virtual tag value in the L1 storage of virtual tags comprises identifying an association between the virtual tag value and an identified way of the respective plurality of ways of an identified cache set of the plurality of cache sets; and
wherein the snoop access circuitry is configured to update the L1 storage of virtual tags subject to identifying that the location in the L1 storage of physical tags where the physical tag value was identified corresponds to the identified way associated with the virtual tag value.
12 . The computing system of claim 1 , wherein the L1 access controller is further configured to, upon an unsuccessful look up of the physical tag value in the L1 storage of physical tags when executing the L1 snoop access, respond to the load operation according to an outcome of another access to a next memory level after the L1 cache.
13 . The computing system of claim 1 , further comprising a load operation queue for storing one or more pending load operations;
wherein the L1 access controller is configured to receive the load operation from the load operation queue; and
wherein the L1 aliasing snoop to the L1 cache is performed concurrently with the L1 access controller accessing the L1 cache in response to another load operation received from the load operation queue.
14 . The computing system of claim 1 , further comprising a translation circuitry configured to translate virtual memory addresses to physical memory addresses;
wherein the first physical memory address is computed by the translation circuitry using the virtual memory address.
15 . The computing system of claim 14 , wherein the translation circuitry is a memory management unit.
16 . The computing system of claim 1 ,
wherein the computing system further comprises a snoop filter storage comprising a plurality of filter entries, each filter entry of the plurality of filter entries corresponding to one of the first plurality of cache lines; and
wherein performing the L1 aliasing snoop is subject to:
computing an address identification value using the first physical memory address; and
identifying the address identification value in the snoop filter storage.
17 . The computing system of claim 16 , wherein computing the address identification value comprises applying a hash function to the first physical memory address.
18 . The computing system of claim 1 , wherein the L1 access controller is further configured to:
in response to a store operation comprising the virtual memory address, access the L1 cache to perform the store operation using the physical tag value computed using the first physical memory address.
19 . A method for memory caching, comprising:
receiving from at least one first processing circuitry a load operation comprising a virtual memory address,
accessing a lower level (L1) cache associated with at least one first processing circuitry to perform the load operation, where the L1 cache is configured to store a first plurality of cache lines and comprises a storage of virtual tags (L1 storage of virtual tags) and a storage of physical tags (L1 storage of physical tags), where each of the first plurality of cache lines is identified for load operations by a first virtual tag in the L1 storage of virtual tags and for store operations by a first physical tag in the L1 storage of physical tags, where performing the load operation comprises looking up in the L1 storage of virtual tags a virtual tag value computed using the virtual memory address;
upon failing to identify the virtual tag value in the L1 storage of virtual tags (L1 virtual miss), providing the load operation to a lower cache miss controller circuitry (L1 miss controller), otherwise, upon identifying the virtual tag value, data is received directly from the cache; and
initiating by the L1 miss controller another access to the L1 cache (L1 aliasing snoop) by a snoop access circuitry, the L1 aliasing snoop comprising looking up in the L1 storage of physical tags a physical tag value computed using a first physical memory address corresponding to the virtual memory address.
20 . A processor comprising:
a lower level (L1) cache associated with at least one first processing circuitry, configured to store a first plurality of cache lines and comprising a storage of virtual tags (L1 storage of virtual tags) and a storage of physical tags (L1 storage of physical tags), where each of the first plurality of cache lines is identified for load operations by a first virtual tag in the L1 storage of virtual tags and for store operations by a first physical tag in the L1 storage of physical tags;
a lower cache access controller circuitry (L1 access controller), configured to access the L1 cache by the at least one first processing circuitry;
a snoop access circuitry associated with the at least one first processing circuitry, configured to access the L1 cache by at least one second processing circuitry; and
a lower cache miss controller circuitry (L1 miss controller);
wherein the L1 access controller is further configured to, in response to receiving from the at least one first processing circuitry a load operation comprising a virtual memory address:
access the L1 cache (L1 access) to perform the load operation comprising looking up in the L1 storage of virtual tags a virtual tag value computed using the virtual memory address; and
upon failing to identify the virtual tag value in the L1 storage of virtual tags (L1 virtual miss), provide the load operation to the L1 miss controller, and
wherein the L1 miss controller is configured to, in response to receiving the load operation from the L1 access controller, initiate another access to the L1 cache (L1 aliasing snoop) by the snoop access circuitry, the L1 aliasing snoop comprising looking up in the L1 storage of physical tags a physical tag value computed using a first physical memory address corresponding to the virtual memory address.