Low power area efficient adaptive load compensation
Systems and methods for load compensation are presented to support a wide range of capacitive loads on a pad coupled to an I/O transmitter. The I/O transmitter includes I/O architecture coupled to a pad and a calibration circuit coupled to the I/O architecture. The calibration circuit includes sensing circuitry, pulse generation circuitry coupled to the sensing circuitry and control bit generation circuitry coupled to the pulse generation circuitry. The control bit generation circuitry generates control bits proportional to load variations detected at the pad and feeds the control bits to the I/O architecture to modulate rise and fall times of pulsed signals at the pad.
1 . A input/output (I/O) transmitter comprising:
I/O architecture coupled to a pad; and
a calibration circuit coupled to the I/O architecture, the calibration circuit including:
sensing circuitry including a resistor ladder coupled to a comparator, wherein the resistor ladder generates a reference signal and the comparator detects when a voltage at the pad crosses the reference signal;
pulse generation circuitry coupled to the sensing circuitry, the pulse generation circuitry including a plurality of serial delay elements that generate a sequence of time-offset pulses until the comparator detects that the voltage at the pad crosses the reference signal; and
control bit generation circuitry coupled to the pulse generation circuitry, wherein the control bit generation circuitry generates control bits based on a duration between initiation of a pad transition and detection of the reference signal crossing and feeds the control bits to the I/O architecture to modulate rise and fall times of pulsed signals at the pad.
2 . The I/O transmitter of claim 1 , wherein the I/O architecture includes a logic level shifter, pre-drivers, and drivers, wherein the pre-drivers and the drivers receive the control bits generated by the control bit generation circuitry to modulate the rise and fall times of the pulsed signals at the pad.
3 . The I/O transmitter of claim 1 , wherein the sensing circuitry is gated with disable signals to prevent direct current (DC) before and after calibration is performed by the calibration circuit.
4 . The I/O transmitter of claim 1 , wherein the resistor ladder generates the reference signal based on a rise time measurement threshold of an interface protocol.
5 . The I/O transmitter of claim 1 , wherein the plurality of serial delay elements generate sequential pulses that are gated by an output of the comparator such that generation of the pulses stops when the voltage at the pad crosses the reference signal.
6 . The I/O transmitter of claim 5 , wherein the sequential pulses generated by the plurality of serial delay elements are provided to a plurality of latches that capture and store the pulses prior to termination of the pulse generation.
7 . The I/O transmitter of claim 1 , wherein the calibration circuit further includes disable generation circuitry to disable the sensing circuitry and the control bit generation circuitry when modulation of the rise and fall times of the pulsed signals at the pad is complete.
8 . The I/O transmitter of claim 7 , wherein the disable generation circuitry includes an inverter, a delay element, and a one-bit counter.
9 . The I/O transmitter of claim 1 , wherein the control bit generation circuitry includes a plurality of latches for storing a respective control bit.
10 . A calibration circuit comprising:
sensing circuitry including a resistor ladder coupled to a comparator, wherein the resistor ladder generates a reference signal and the comparator detects when a voltage at the pad crosses the reference signal;
pulse generation circuitry coupled to the sensing circuitry, the pulse generation circuitry including a plurality of serial delay elements that generate a sequence of time-offset pulses until the comparator detects that the voltage at the pad crosses the reference signal; and
control bit generation circuitry coupled to the pulse generation circuitry, wherein the control bit generation circuitry generates control bits based on a duration between initiation of a pad transition and detection of the reference signal crossing to modulate rise and fall times of pulsed signals input to the device.
11 . The calibration circuit of claim 10 , wherein the sensing circuitry is gated with disable signals to prevent direct current (DC) before and after calibration is performed by the calibration circuit.
12 . The calibration circuit of claim 10 , wherein the resistor ladder generates the reference signal based on a rise time measurement threshold of an interface protocol.
13 . The calibration circuit of claim 10 , wherein the plurality of serial delay elements generate sequential pulses that are gated by an output of the comparator such that generation of the pulses stops when the voltage at the pad crosses the reference signal.
14 . The calibration circuit of claim 13 , wherein the sequential pulses generated by the plurality of serial delay elements are provided to a plurality of latches that capture and store the pulses prior to termination of the pulse generation.
15 . The calibration circuit of claim 10 , wherein the calibration circuit further includes disable generation circuitry to disable the sensing circuitry and the control bit generation circuitry when modulation of the rise and fall times of the pulsed signals at the device is complete.
16 . The calibration circuit of claim 15 , wherein the disable generation circuitry includes an inverter, a delay element, and a one-bit counter.
17 . The calibration circuit of claim 10 , wherein the control bit generation circuitry includes a plurality of latches for storing a respective control bit.
18 . A method comprising:
feeding an input/output (I/O) architecture coupled to a pad with pulsed input signals;
detecting load variations at the pad by generating a reference signal using a resistor ladder and detecting, using a comparator, when a voltage at the pad crosses the reference signal;
measuring rise and fall times of pulsed signals at the pad by generating, using a plurality of serial delay elements, a sequence of time-offset pulses until the comparator detects that the voltage at the pad crosses the reference signal;
generating, using control bit generation circuitry, control bits based on a duration between initiation of a pad transition and detection of the reference signal crossing; and
feeding, using a calibration circuit, the control bits to the I/O architecture to modulate rise and fall times of the pulsed signals at the pad.
19 . The method of claim 18 , wherein the sensing circuitry is gated with disable signals to prevent direct current (DC) before and after calibration is performed by the calibration circuit coupled to the I/O architecture.
20 . The method of claim 19 , further comprising disabling, using disable generation circuitry, the sensing circuitry and the control bit generation circuitry when modulation of the rise and fall times of the pulsed signals at the pad is complete.