IP Library › Granted Patent US 12681872

Granted Patent B2

US 12681872 · App. 17/846,522 · Granted Jul 14, 2026

Memory manager, processor memory subsystem, processor, and electronic device

Inventor: Wen Yin (Shenzhen, CN)

Assignee: HUAWEI TECHNOLOGIES CO., LTD.

G06F13/1668 G06F12/0862 G06F13/387 G06F13/4282

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Quick Facts

Patent No.: US 12681872
App. No.: 17/846,522
Granted: Jul 14, 2026
Kind: B2

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Abstract

A memory manager disposed between a memory and a processor. One end of the memory manager is coupled to the processor using a serial line, and the other end of the memory manager is coupled to the memory using a parallel line to provide the processor with a serial interface instead of a parallel interface.

Claims (109)

1 . A memory manager configured to control data exchange between a processor and a memory, and comprising:

a parallel interface circuit comprising:

an internal connection end; and

an external connection end configured to couple to the memory;

a cache prefetching circuit;

a memory control circuit coupled to the cache prefetching circuit, configured to control an on state and an off state of the cache prefetching circuit, and comprising:

a first end; and

a second end coupled to the internal connection end; and

a serial-to-parallel conversion interface circuit comprising:

a serial end configured to couple to the processor; and

a parallel end coupled to the first end and the internal connection end, wherein the serial-to-parallel conversion interface circuit is configured to:

receive, from the processor, a serialized memory data write request;

convert the serialized memory data write request into a parallelized memory data write request; and

send, to the memory control circuit, the parallelized memory data write request, wherein the cache prefetching circuit is coupled to the parallel end of the serial-to-parallel conversion interface circuit and the internal connection end of the parallel interface circuit, and wherein the memory control circuit is further configured to:

selectively route data between the serial-to-parallel conversion interface circuit and the parallel interface circuit through the cache prefetching circuit in response to the cache prefetching circuit being in the on state; and

bypass the cache prefetching circuit such that the parallel interface circuit is directly coupled to the serial-to-parallel conversion interface circuit in response to the cache prefetching circuit being in the off state.

2 . The memory manager of claim 1 , wherein the cache prefetching circuit is configured to prefetch data from the memory and store the data.

3 . The memory manager of claim 2 , wherein the serial-to-parallel conversion interface circuit is configured to:

receive, from the processor, a serialized cache data read request;

convert the serialized cache data read request into a parallelized cache data read request; and

send, to the cache prefetching circuit, the parallelized cache data read request,

wherein the cache prefetching circuit is configured to send, to the serial-to-parallel conversion interface circuit, parallelized first data corresponding to the parallelized cache data read request, and

wherein the serial-to-parallel conversion interface circuit is further configured to:

convert the parallelized first data into serialized first data; and

send, to the processor, the serialized first data.

4 . The memory manager of claim 2 , wherein the serial-to-parallel conversion interface circuit is configured to:

receive, from the processor, a serialized memory data read request;

convert the serialized memory data read request into a parallelized memory data read request; and

send, to the memory control circuit, the parallelized memory data read request,

wherein the memory control circuit is configured to send, using the parallel interface circuit, the parallelized memory data read request to the memory,

wherein the cache prefetching circuit is configured to:

receive, from the memory, parallelized second data corresponding to the parallelized memory data read request; and

send, to the serial-to-parallel conversion interface circuit, the parallelized second data, and

wherein the serial-to-parallel conversion interface circuit is further configured to:

convert the parallelized second data into serialized second data; and

send, to the processor, the serialized second data.

5 . The memory manager of claim 4 , wherein the cache prefetching circuit is further configured to store the parallelized second data.

6 . The memory manager of claim 1 , wherein the memory control circuit is configured to send, using the parallel interface circuit, the parallelized memory data write request to the memory.

7 . The memory manager of claim 6 , wherein the cache prefetching circuit is further configured to:

prefetch, from the memory, processed data obtained through a write operation corresponding to the parallelized memory data write request; and

store the processed data.

8 . A processor memory subsystem, comprising:

a first processor comprising a first serial-to-parallel conversion interface circuit having a first serial end;

a first memory;

a first memory manager comprising:

a parallel interface circuit comprising:

an internal connection end; and

an external connection end configured to couple to the first memory;

a cache prefetching circuit;

a memory control circuit coupled to the cache prefetching circuit, configured to control an on state and an off state of the cache prefetching circuit and to control data exchange between the first processor and the first memory, and comprising:

a first end; and

a second end coupled to the internal connection end; and

a second serial-to-parallel conversion interface circuit comprising:

a second serial end configured to couple to the first serial end; and

a parallel end coupled to the first end and the internal connection end,

wherein the cache prefetching circuit is coupled to the parallel end of the serial-to-parallel conversion interface circuit and the internal connection end of the parallel interface circuit, and

wherein the memory control circuit is further configured to:

a second processor is configured to send, using an input/output interface circuit, a parallelized memory data write request to a third processor, wherein the third processor comprises a third serial-to-parallel conversion interface circuit and is configured to:

convert, using the third serial-to-parallel conversion interface circuit, the parallelized memory data write request into a serialized memory data write request; and

send, to a second memory manager and corresponding to the third processor, the serialized memory data write request.

9 . The processor memory subsystem of claim 8 , further comprising:

a plurality of memories;

a plurality of memory managers, wherein each of the memory managers is coupled to one of the memories; and

two processors comprising a second processor and a third processor coupled to each other using an input/output interface circuit, wherein each of the two processors is coupled to one or more of the memory managers.

10 . The processor memory subsystem of claim 9 , wherein the second processor is configured to send, using the input/output interface circuit, a parallelized cache data read request to the third processor, and wherein the third processor comprises a third serial-to-parallel conversion interface circuit and is configured to:

convert, using the third serial-to-parallel conversion interface circuit, the parallelized cache data read request into a serialized cache data read request; and

send, to a second memory manager in the memory managers and corresponding to the third processor, the serialized cache data read request.

11 . The processor memory subsystem of claim 9 , wherein the second processor is configured to send, using the input/output interface circuit, a parallelized memory data read request to the third processor, and wherein the third processor comprises a third serial-to-parallel conversion interface circuit and is configured to:

convert, using the third serial-to-parallel conversion interface circuit, the parallelized memory data read request into a serialized memory data read request; and

send, to a second memory manager in the memory managers and corresponding to the third processor, the serialized memory data read request.

12 . The processor memory subsystem of claim 9 , wherein the first processor is configured to:

receive, from the one or more of the memory managers, serialized data;

convert, using the first serial-to-parallel conversion interface circuit, the serialized data into parallelized data; and

send, to the third processor using the input/output interface circuit, the parallelized data.

13 . The processor memory subsystem of claim 9 , wherein the first memory manager is integrated into the first processor.

14 . The processor memory subsystem of claim 9 , wherein the first memory manager is independent of each of the first processor and the first memory.

15 . An electronic device comprising:

a processor memory subsystem comprising:

a processor comprising a first serial-to-parallel conversion interface circuit having a first serial end;

a memory; and

a memory manager comprising:

a parallel interface circuit comprising:

an internal connection end; and

an external connection end configured to couple to the memory;

a cache prefetching circuit;

a memory control circuit coupled to the cache prefetching circuit, configured to control an on state and an off state of the cache prefetching circuit and to control data exchange between the processor and the memory, wherein the memory control circuit comprises:

a first end; and

a second end coupled to the internal connection end; and

a serial-to-parallel conversion interface circuit comprising:

a second serial end configured to couple to the first serial end; and

a parallel end coupled to the first end and the internal connection end,

wherein the serial-to-parallel conversion interface circuit is configured to:

receive, from the processor, a serialized memory data write request;

convert the serialized memory data write request into a parallelized memory data write request; and

send, to the memory control circuit, the parallelized memory data write request,

wherein the cache prefetching circuit is coupled to the parallel end of the serial-to-parallel conversion interface circuit and the internal connection end of the parallel interface circuit, and

wherein the memory control circuit is further configured to:

16 . The electronic device of claim 15 , wherein the processor memory subsystem further comprises:

a plurality of memories;

a plurality of memory managers, wherein each of the memory managers is coupled to one of the memories; and

two processors coupled to each other using an input/output interface circuit, wherein each of the two processors is coupled to one or more of the memory managers.

17 . The electronic device of claim 15 , wherein the memory manager is integrated into the processor.

18 . The electronic device of claim 15 , wherein the memory manager is independent of each of the processor and the memory.

19 . The electronic device of claim 15 , wherein the cache prefetching circuit is configured to prefetch data from the memory and store the data.

20 . The electronic device of claim 15 , wherein the memory control circuit is configured to send, using the parallel interface circuit, the parallelized memory data write request to the memory.