Topology-based dynamic address assignment of semiconductor memory devices
Disclosed are methods, systems, and apparatuses for a topology-based dynamic address assignment (DAA) of semiconductor memory devices (e.g., dynamic random access memory (DRAM)). The memory devices may be connected via a daisy chain arrangement that forms a sideband bus. During a DAA process, the topology-based DAA assigns addresses to the memory devices based on their placement on the daisy chain (e.g., their placement within the topology of the sideband bus). The topology-based DAA described herein may facilitate predictably assigning dynamic addresses to memory devices based on, for example, their position on a memory module.
1 . A memory device comprising:
a memory array;
a sideband bus interface coupled to a sideband bus, the sideband bus interface comprising:
an upstream data terminal coupled to an upstream data line; and
a downstream data terminal coupled to a downstream data line, wherein the upstream data line is initially uncoupled communicatively from the downstream data line; and
a topology-based dynamic address assignment (DAA) circuit coupled to the sideband bus interface, wherein the topology-based DAA circuit is configured to:
determine whether the memory device has been assigned an address; and
couple the upstream data line to the downstream data line when the memory device has been assigned the address, the upstream and downstream data lines coupled for allowing a message to flow across the downstream and upstream data lines regardless of a content of the message.
2 . The memory device of claim 1 , the memory device further comprising a dynamic address valid register, wherein the determination of whether the memory device has been assigned an address is based on a value of the dynamic address valid register.
3 . The memory device of claim 1 , wherein the topology-based DAA circuit is further configured to drive a static value on the downstream data line when the memory device has not been assigned an address.
4 . The memory device of claim 3 , wherein the static value is a logical high value.
5 . The memory device of claim 1 , wherein the address identifies the memory device on the sideband bus.
6 . The memory device of claim 1 , wherein the topology-based DAA circuit comprises a transmission gate coupled to the upstream data line and the downstream data line, and wherein coupling the upstream data line to the downstream data line comprises enabling the transmission gate.
7 . The memory device of claim 1 , wherein the topology-based DAA circuit is further configured to:
receive an enter DAA command over the upstream data line; and
based on determining that the memory device has not been assigned an address, performing a DAA process in response to receiving the enter DAA command, the DAA process comprising:
transmitting device information, associated with the memory device, over the upstream data line;
receiving a dynamic address over the upstream data line; and
maintaining the dynamic address as the address assigned to the memory device.
8 . The memory device of claim 1 , wherein the downstream data line is coupled to an upstream data terminal of a second memory device.
9 . The memory device of claim 1 , wherein the upstream data line is coupled to a data terminal of a bus controller.
10 . The memory device of claim 1 , wherein the sideband bus complies with a portion of an Improved Inter Integrated Circuit (I3C) specification.
11 . The memory device of claim 1 wherein the memory device comprises a dynamic random access memory (DRAM) device, the memory device further comprising a mode register, wherein the mode register characterizes an aspect of the memory array, and wherein the memory device is configured to transmit a value from the mode register over the sideband bus.
12 . A memory module comprising:
a first memory device, the first memory device comprising a first clock terminal, a first upstream data terminal, and a first downstream data terminal;
a second memory device, the second memory device comprising a second clock terminal, a second upstream data terminal, and a second downstream data terminal;
a clock line coupled to the first clock terminal and the second clock terminal;
a first data line segment coupled to the first upstream data terminal; and
a second data line segment coupled to the first downstream data terminal and the second upstream data terminal;
wherein, prior to an address being assigned to the first memory device, the first upstream data terminal is initially uncoupled from the first downstream data terminal; and
wherein, when the first memory device has been assigned the address, the first memory device is configured to couple the first upstream data terminal to the first downstream data terminal for allowing a message to flow across the first upstream data terminal and the first downstream data terminal regardless of a content of the message.
13 . The memory module of claim 12 , wherein the first data line segment is coupled to a data terminal of a bus controller.
14 . The memory module of claim 13 , wherein the bus controller is a memory controller.
15 . The memory module of claim 12 , wherein the first memory device comprises a topology-based DAA circuit, the topology-based DAA circuit configured to couple the first upstream data terminal to the first downstream data terminal when the first memory device is associated with an assigned address.
16 . The memory module of claim 15 , wherein the topology-based DAA circuit is further configured to drive a static value on the second data line segment when the first memory device is not associated with an assigned address.
17 . The memory module of claim 12 , the memory module further comprising a sideband bus comprised of the clock line, the first data line segment, and the second data line segment.
18 . The memory module of claim 17 , the memory module further comprising a temperature sensor coupled to a second sideband bus.
19 . A method comprising:
transmitting, by a bus controller coupled to a bus, an enter DAA command over the bus;
receiving, over the bus, device information from a memory device coupled to the bus;
maintaining an upstream data terminal of the memory device uncoupled from a downstream data terminal of the memory device until the memory device receives a dynamic address;
generating, by the bus controller, the dynamic address;
associating the dynamic address with the received device information;
transmitting, over the bus, the dynamic address to the memory device;
coupling, after the memory device receives the dynamic address, the upstream data terminal to the downstream data terminal to allow the dynamic address to flow across the upstream data terminal and the downstream data terminal regardless of a content of the dynamic address; and
transmitting, over the bus, the enter DAA command.
20 . The method of claim 19 , wherein the generated dynamic address is a next sequential address of a previously generated dynamic address.