Method and apparatus for cache tiering

1 . A method for use in a storage processor, comprising:

receiving an I/O request that is associated with a logical block address;

allocating, in a global memory, a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and

executing the I/O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot,

wherein the global memory includes a random access memory (RAM) portion, a controller memory buffer (CMB) portion, and a persistent memory region (PMR) portion that are unified in a peripheral component interconnect (PCI) address space that is global to a storage array of which the storage processor is part, the RAM portion being implemented by using RAM hardware in at least two storage processors in the storage array, the CMB portion being implemented by using volatile memory hardware in at least two storage drives that are part of the storage array, and the PMR portion being implemented by using non-volatile memory hardware in at least two storage drives that are part of the storage array,

wherein identifying the type of memory that is required to host the cache slot includes selecting one of the RAM, PMR, or CMB portions of the global memory; and

wherein the configuration settings that are associated with the cache slot specify a policy for identifying the type of memory, the policy specifying at least one of (i) a maximum allowable individual utilization level which the RAM portion must have and still be eligible for selection, and (ii) a maximum individual utilization level which the CMB portion may have and still be eligible for selection.

2 . The method of claim 1 , wherein the I/O request is received from a host device, and the type of memory is selected based on an identifier of the host device.

3 . The method of claim 1 , further comprising:

adding a first memory region to a physical address map, the first memory region forming at least a part of the RAM portion;

adding a second memory region to the physical address map, the second memory region forming at least a part of the CMB portion; and

generating a cache metadata table that identifies a plurality of cache slots, at least a first one of the plurality of cache slots corresponding to a portion of the first memory region, and at least a second one of the plurality of cache slots corresponding to a portion of the second memory region.

4 . The method of claim 1 , wherein direct memory access (DMA) writes to each of the RAM portion, the CMB portion, and the PMR portion are synchronized by using Peterson locks to ensure cache coherency.

5 . The method of claim 1 , wherein the policy is further based on a level of a subscription plan of a user associated with the I/O request.

6 . The method of claim 1 , wherein the policy provides that the PMR portion should be selected only if criteria for selecting the RAM portion and the CMB portion are not met.

7 . A computing device comprising:

at least one processor that is configured to perform the operations of:

receiving an I/O request that is associated with a logical block address;

allocating, in a global memory, a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and

executing the I/O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot,

wherein the global memory includes a random access memory (RAM) portion, a controller memory buffer (CMB) portion, and a persistent memory res ion (PMR) portion that are unified in a peripheral component interconnect (PCI) address space that is global to a storage array of which the storage processor is part, the RAM portion being implemented by using RAM hardware in at least two storage processors in the storage array, the CMB portion being implemented by using volatile memory hardware in at least two storage drives that are part of the storage array, and the PMR portion being implemented by using non-volatile memory hardware in at least two storage drives that are part of the storage array,

wherein identifying the type of memory that is required to host the cache slot includes selecting one of the RAM, PMR, or CMB portions of the global memory, and

wherein the configuration settings that are associated with the cache slot specify a policy for identifying the type of memory, the policy specifying at least one of (i) a maximum allowable individual utilization level which the RAM portion must have and still be eligible for selection, and (ii) a maximum individual utilization level which the CMB portion may have and still be eligible for selection.

8 . The computing device of claim 7 , wherein the I/O request is received from a host device, and the type of memory is selected based on an identifier of the host device.

9 . The computing device of claim 7 , further comprising:

adding a first memory region to a physical address map, the first memory region forming at least a part of the RAM portion;

adding a second memory region to the physical address map, the second memory region forming at least a part of the CMB portion; and

generating a cache metadata table that identifies a plurality of cache slots, at least a first one of the plurality of cache slots corresponding to a portion of the first memory region, and at least a second one of the plurality of cache slots corresponding to a portion of the second memory region.

10 . The computing device of claim 7 , wherein direct memory access (DMA) writes to each of the RAM portion, the CMB portion, and the PMR portion are synchronized by using Peterson locks to ensure cache coherency.

11 . The computing device of claim 7 , wherein the policy is further based on a level of a subscription plan of a user associated with the I/O request.

12 . The computing device of claim 7 , wherein the policy provides that the PMR portion should be selected only if criteria for selecting the RAM portion and the CMB portion are not met.

13 . A non-transitory computer-readable medium storing one or more processor-executable instructions, which, when executed by at least one processor of a computing device, cause the computing device to perform the operations of:

receiving an I/O request that is associated with a logical block address;

allocating, in a global memory, a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and

executing the I/O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot,

wherein the global memory includes a random access memory (RAM) portion, a controller memory buffer (CMB) portion, and a persistent memory region (PMR) portion that are unified in a peripheral component interconnect (PCI) address space that is global to a storage array of which the storage proc s part, the RAM portion being implemented by using RAM hardware in at least two storage processors in the storage array, the CMB portion being implemented by using volatile memory hardware in at least two storage drives that are part of the storage array, and the PMR portion being implemented by using non-volatile memory hardware in at least two storage drives that are part of the storage array,

wherein identifying the type of memory that is required to host the cache slot includes selecting one of the RAM, PMR, or CMB portions of the global memory, and

wherein the configuration settings that are associated with the cache slot specify a policy for identifying the type of memory, the policy specifying at least one of (i) a maximum allowable individual utilization level which the RAM portion must have and still be eligible for selection, and (ii) a maximum individual utilization level which the CMB portion may have and still be eligible for selection.

14 . The non-transitory computer-readable medium of claim 13 , wherein the I/O request is received from a host device, and the type of memory is selected based on an identifier of the host device.

15 . The non-transitory computer-readable medium of claim 13 , further comprising:

adding a first memory region to a physical address map, the first memory region forming at least a part of the RAM portion;

adding a second memory region to the physical address map, the second memory region forming at least a part of the CMB portion; and

generating a cache metadata table that identifies a plurality of cache slots, at least a first one of the plurality of cache slots corresponding to a portion of the first memory region, and at least a second one of the plurality of cache slots corresponding to a portion of the second memory region.