Bus protocol for multiple chipsets
Circuits, methods, and apparatus that can allow chipsets in an electronic device to share information such that they can more efficiently utilize resources that are available in the electronic device. One example can provide a bus that is shared by three or more chipsets in an electronic device. This shared bus can be used by the chipsets in the electronic device to communicate and negotiate for the utilization of resources of the electronic device.
1 . An electronic device comprising:
a first chipset that utilizes a first frequency range;
a second chipset that utilizes a second frequency range at least partially overlapping the first frequency range; and
an inter-chipset bus communicatively coupled to the first chipset and the second chipset, and configured to transfer, between the first chipset and the second chipset, one or more messages that negotiate for use of the first frequency range and the second frequency range.
2 . The electronic device of claim 1 further comprising:
a third chipset, wherein
the inter-chipset bus is coupled to the third chipset, and
the inter-chipset bus is configured to convey one or more messages between the first chipset and the third chipset and one or more messages between the second chipset and the third chipset that negotiate for use of one or more shared resources.
3 . The electronic device of claim 1 , wherein the one or more messages contain priority information.
4 . The electronic device of claim 1 , wherein
the first chipset is configured to generate radio-frequency signals that utilize the first frequency range, and
the second chipset is configured to generate radio-frequency signals that utilize the second frequency range.
5 . The electronic device of claim 1 , wherein, based on the one or more messages, the first chipset is configured to send radio-frequency signals that utilize the first frequency range in a first time slot and the second chipset is configured to send radio-frequency signals that utilize the second frequency range in a second time slot.
6 . The electronic device of claim 1 , wherein
the first chipset is configured to receive radio-frequency signals that utilize the first frequency range, and
the second chipset is configured to receive radio-frequency signals that utilize the second frequency range.
7 . The electronic device of claim 1 , wherein, based on the one or more messages, the first chipset is configured to receive radio-frequency signals that utilize the first frequency range in a first time slot and the second chipset is configured to receive radio-frequency signals that utilize the second frequency range in a second time slot.
8 . The electronic device of claim 1 further comprising:
an antenna coupled to the first chipset and the second chipset, wherein the inter-chipset bus is configured to transfer one or more additional messages between the first chipset and the second chipset that negotiate for use of the antenna.
9 . The electronic device of claim 1 further comprising:
a memory coupled to the first chipset and the second chipset, wherein the inter-chipset bus is configured to transfer one or more additional messages between the first chipset and the second chipset that negotiate for use of the memory.
10 . The electronic device of claim 1 further comprising:
a battery coupled to the first chipset and the second chipset, wherein the inter-chipset bus is configured to transfer one or more additional messages between the first chipset and the second chipset that negotiate for use of the battery.
11 . The electronic device of claim 10 , wherein, based on the one or more additional messages, the first chipset and the second chipset are configured to draw power exceeding a threshold from the battery at different times.
12 . The electronic device of claim 1 , wherein the inter-chipset bus is configured to transfer one or more additional messages between the first chipset and the second chipset that negotiate for use of transmit power.
13 . An electronic device comprising:
a chipset for wireless communication that includes an auto-response buffer configured to store state information of the chipset and to be powered on when the chipset is powered down or in a sleep state; and
an inter-chipset bus communicatively coupled to the chipset, wherein the state information is accessible from the auto-response buffer via the inter-chipset bus when the chipset is powered down or in the sleep state.
14 . The electronic device of claim 13 further comprising:
an additional chipset coupled to the inter-chipset bus and configured to obtain the state information of the chipset from the auto-response buffer when the chipset is powered down or in the sleep state.
15 . The electronic device of claim 13 , wherein the chipset includes a storage circuit configured to store messages from one or more other chipsets received via the inter-chipset bus.
16 . An electronic device comprising:
a first chipset for wireless communication;
a second chipset for wireless communication;
a third chipset; and
a shared bus communicatively coupled to the first chipset, the second chipset, and the third chipset, and configured to transfer, between the first chipset and the second chipset, one or more messages that include an indication of transmit or receive activity at the first chipset and an indication of a used bandwidth and that negotiate for use of one or more resources shared between the first chipset and the second chipset.
17 . The electronic device of claim 16 , wherein
the first chipset has a first storage circuit that stores messages received from the second chipset via the shared bus, and
the first chipset has a second storage circuit that stores messages received from the third chipset via the shared bus.
18 . The electronic device of claim 16 , wherein
the first chipset has a storage circuit that stores state information for the first chipset, and
the second chipset and the third chipset are each configured to obtain the state information via the shared bus.
19 . The electronic device of claim 16 , wherein
the first chipset has first and second input-output pins coupled to the shared bus,
the second chipset has first and second input-output pins coupled to the shared bus, and
the third chipset has first and second input-output pins coupled to the shared bus.
20 . The electronic device of claim 16 , wherein the one or more messages between the first chipset and the second chipset include a timing of an activity envelope.