Port control in a parallel multi-port system

1 . A parallel multiple-port system, comprising:

a plurality of ports;

a plurality of processors; and

a memory storing software code which, when executed by the plurality of processors, causes the processors to control the plurality of ports,

wherein the plurality of processors has a first processor that is configured to control a first port of the plurality of ports,

wherein the plurality of processors has a second processor that is different from the first processor and is configured to control a second port of the plurality of ports different from the first port,

wherein the software code comprises a common software code portion relevant to the plurality of ports and for execution by the plurality of processors, and

wherein the software code further comprises a port specific code portion comprising first configuration data for the first port and for execution by the first processor, the port specific code portion further comprising second configuration data for the second port and for execution by the second processor.

2 . The parallel multiple-port system according to claim 1 , further comprising:

a plurality of port controllers, wherein each port controller is configured to control one of the plurality of ports, and

wherein the plurality of processors are configured to control the ports via the plurality of port controllers.

3 . The parallel multiple-port system according to claim 1 ,

wherein the first processor is configured to control a first subset of the plurality of ports, and

wherein the second processor is configured to control a second subset of the plurality of ports.

4 . The parallel multiple-port system according to claim 1 ,

wherein the common software code portion comprises boot codes,

wherein the boot codes links each processor to a memory address in the port specific code portion, and

wherein the memory address points to configuration data of one port.

5 . The parallel multiple-port system according to claim 1 ,

wherein the common software code portion comprises function codes,

and wherein the function codes comprises a generic program of the parallel multi-port system without processor or port identifications.

6 . The parallel multiple-port system according to claim 1 , wherein the ports are charging ports.

7 . The parallel multiple-port system according to claim 2 ,

wherein the first processor is configured to control a first subset of the plurality of ports, and

wherein the second processor is configured to control a second subset of the plurality of ports.

8 . The parallel multiple-port system according to claim 2 ,

wherein the common software code portion comprises boot codes,

wherein the boot codes link each processor to a memory addresses in the port specific code portion, and

wherein the memory address points to configuration data of one port.

9 . The parallel multiple-port system according to claim 2 ,

wherein the common software code portion comprises function codes,

and wherein the function codes comprises a generic program of the parallel multi-port system without processor or port identifications.

10 . The parallel multiple-port system according to claim 2 , wherein the ports are charging ports.

11 . The parallel multiple-port system according to claim 6 , further comprising a plurality of power loops, wherein each power loop is configured to provide power to one of the charging ports.

12 . The parallel multiple-port system according to claim 6 , wherein the ports are USB ports.

13 . The parallel multiple-port system according to claim 11 , wherein the ports are USB ports.

14 . A computer program stored in a non-volatile computer executable program memory comprising instructions which, when the program is executed by a plurality of processors of a parallel multi-port system, cause the plurality of processors to control a plurality of ports, cause a first processor of the plurality of processors to control a first port, and cause a second processor of the plurality of processors different from the first processor to control a second port different from the first port,

wherein the program comprises a common software code portion relevant to the plurality of ports and for execution by the plurality of processors, and

wherein the program further comprises a port specific code portion comprising first configuration data for the first port and for execution by the first processor, the port specific code portion further comprising second configuration data for the second port and for execution by the second processor.

15 . The computer program according to claim 14 ,

wherein the common software code portion comprises boot codes,

wherein the boot codes links each processor to a memory addresses in the port specific code portion, and

wherein the memory address links to configuration data of one port.

16 . The computer program according to claim 14 ,

wherein the common software code portion comprises function codes,

and wherein the function codes comprises a generic program of the parallel multi-port system without processor or port identifications.

17 . The computer program according to claim 15 ,

wherein the common software code portion comprises function codes,

and wherein the function codes comprises a generic program of the parallel multi-port system without processor or port identifications.