Transactional memory support for Compute Express Link (CXL) devices

1 . An apparatus comprising:

a port to couple to a host processor over a Compute Express Link (CXL)-based link;

a transaction queue to queue memory transactions to be completed in an addressable memory coupled to the apparatus;

a transaction cache;

conflict detection circuitry to determine whether a conflict exists between memory transactions based on coherence traffic on the CXL-based link; and

transaction execution circuitry to:

access a transaction from the transaction queue, the transaction to implement one or more memory operations in the memory;

store records of each respective operation of the transaction and data from the memory to be accessed by the operations in the transaction cache;

execute operations of the transaction, including modifying data stored in the transaction cache; and

based on completion of the transaction, cause the modified data from the transaction cache to be stored in the memory.

2 . The apparatus of claim 1 , wherein the transaction is an atomic transaction.

3 . The apparatus of claim 1 , wherein the transaction execution circuitry is to cause a coherence traffic signal to be transmitted to the host processor over the link based on accessing the transaction.

4 . The apparatus of claim 1 , wherein each operation record comprises a unique identifier of the transaction and a unique identifier of the operation within the transaction.

5 . The apparatus of claim 1 , wherein each record comprises store data associated with the operation of the transaction.

6 . The apparatus of claim 1 , wherein the conflict detection circuitry is to interrupt the transaction execution circuitry based on detection of a conflict.

7 . The apparatus of claim 6 , wherein the transaction execution circuitry is to roll back one or more operations of the transaction based on detection of a conflict.

8 . The apparatus of claim 6 , wherein the transaction execution circuitry is to retry one or more operations of the transaction based on detection of a conflict.

9 . The apparatus of claim 1 , wherein the conflict detection circuitry is to detect a conflict based on a coherence traffic signal indicating a write operation to a location in the memory being accessed by the accessed transaction.

10 . The apparatus of claim 1 , wherein the conflict detection circuitry is to flag a transaction in the transaction queue based on detection of a conflict.

11 . The apparatus of claim 1 , further comprising notification circuitry to notify the transaction execution circuitry of a detected conflict.

12 . The apparatus of claim 1 , wherein the addressable memory is directly coupled to the apparatus over a bus.

13 . The apparatus of claim 1 , wherein the addressable memory is coupled to the apparatus over the CXL-based link.

14 . A system comprising:

a host processor;

a peripheral device coupled to the host processor via a Compute Express Link (CXL)-based link; and

memory in a cache coherency domain with the host processor and the peripheral device; and

wherein the peripheral device comprises:

a transaction queue to queue memory transactions to be completed in the memory;

a transaction cache to store records of in-progress operations of the memory transactions; and

transaction execution circuitry to

execute operations of the memory transactions, including modifying data stored in the transaction cache associated with the memory transactions; and

based on completion of the transactions, cause the modified data from the transaction cache to be stored in the memory.

15 . The system of claim 14 , wherein the peripheral device further comprises conflict detection circuitry to determine whether a conflict exists between memory transactions based on coherence traffic on the CXL-based link.

16 . The system of claim 15 , wherein the conflict detection circuitry is to interrupt the transaction execution circuitry based on detection of a conflict.

17 . The system of claim 15 , wherein the transaction execution circuitry is to roll back or retry one or more operations of the transaction based on detection of a conflict by the conflict detection circuitry.

18 . The system of claim 14 , wherein the transaction execution circuitry is to cause coherence traffic signals to be transmitted to the host processor over the CXL-based link based.

19 . The system of claim 14 , wherein the transaction cache is to store records comprising a unique identifier of the transaction, a unique identifier of the operation within the transaction, and data from the memory associated with each operation within the transaction.

20 . A method comprising:

accessing, by transaction execution circuitry of a device coupled to a host device over a Compute Express Link (CXL)-based link, an atomic transaction from a transaction queue of the device, the atomic transaction to be executed in memory coupled to the host device;

store, in a transaction cache of the device, records of each respective operation of the atomic transaction and data from a memory location indicated by the atomic transaction;

execute operations of the transaction, including modifying the data stored in the transaction cache; and

based on completion of the transaction, store the modified data from the transaction cache in the memory.

21 . The method of claim 20 , further comprising detecting, based on coherence traffic on the CXL-based link, whether a conflict exists between the atomic transactions and one or more other transactions to be executed in the memory location.

22 . The method of claim 21 , wherein the conflict detection is based on a coherence traffic signal indicating a write operation of another transaction to the memory location indicated by the atomic transaction.

23 . The method of claim 21 , further comprising:

detecting that a conflict exists; and

retrying one or more operations of the transaction based on the detected conflict.

24 . The method of claim 23 , further comprising rolling back the transaction and notifying the host device of the transaction roll back.