Multipurpose processor card
View Patent ↗The present invention is a multipurpose microprocessor card for use as the central processing unit for the Command and Data Handling of spacecraft (C&DH), instrument and payload (IC&DH), as well as any custom instrument controller. The processor card utilizes a state-of-the-art, radiation hardened processor (e.g., Aeroflex Gaisler GR70 Quad-Core LEON4 SPARC V8 250 Mhz processor) and supports SpaceWire, technical standard balanced voltage digital interface circuit (e.g., RS-422), and MIL-1553B protocols to communicate with other critical cards and instruments throughout the spacecraft bus. The present invention takes advantage of the fast communication between the processor and a space-qualified radiation-hardened field-programmable gate array (FPGA), to involve high-speed peripherals controlled by the FPGA and accessible by the processor. The present invention has a dedicated port to provide its analog telemetry to be monitored by other cards and can generate a power cycle by a communication board or any other entity capable of monitoring same.
1 . A processor board comprising:
a processor; and
a field-programmable gate array (FPGA);
wherein the processor is connected to the FPGA through a peripheral component interconnect (PCI) interface, which connects a first PCI core on the processor to a second PCI core on the FPGA;
wherein the processor is a radiation-hard system-on-chip featuring a quad-core fault-tolerant processor, and which supports a first multi-port SpaceWire router and a plurality of first SpaceWires;
wherein the FPGA has a radiation-hard configuration and includes nonvolatile re-programmable flash technology, and single-event upset (SEU) hardened registers; and
wherein the FPGA supports a second multi-port SpaceWire router and a plurality of second SpaceWires that exceeds a number of the plurality of the first SpaceWires.
2 . The processor board of claim 1 , further comprising:
a plurality of low voltage differential signaling (LVDS) repeaters configured for the plurality of second SpaceWires, with each of the plurality of LVDS repeaters supporting two Space Wire ports.
3 . The processor board of claim 2 , wherein the second multi-port SpaceWire router and the plurality of LVDS repeaters support twelve SpaceWire ports, and the first multi-port SpaceWire router supports eight SpaceWire ports, totaling 20 ports supported by the first multi-port SpaceWire router and the second multi-port SpaceWire router.
4 . The processor board of claim 3 , wherein the processor supports a start-up non-volatile, read-only memory (SUROM) controlled by a programmable read-only memory (PROM) controller.
5 . The processor board of claim 4 , wherein the processor supports a Synchronous Dynamic Random Access Memory (SDRAM), controlled by an SDRAM controller.
6 . The processor board of claim 5 , wherein the processor further comprises:
a plurality of first universal asynchronous receiver/transmitters (UARTs) connected to the processor at a first UART position thereon; and
a plurality of second UARTs connected to the processor at a second UART position thereon.
7 . The processor of claim 6 , further comprising:
a plurality of debug ports which allow communication between a target device and a host for debugging purposes.
8 . The processor board of claim 7 , further comprising:
a SpaceWire debug port connected to the processor; and
a joint test action group (JTAG) debug port connected to the FPGA;
wherein initial loading of the SUROM is performed through one of the SpaceWire debug port or the JTAG debug port.
9 . The processor board of claim 8 , wherein the FPGA further comprises:
a magneto-resistive random-access memory (MRAM), which includes a plurality of non-volatile random-access memories (NVRAM) which serve as a primary program code storage;
wherein the MRAM is accessed by the processor through the FPGA.
10 . The processor board of claim 9 , wherein the FPGA further comprises:
a synchronous dynamic random-access memory (SDRAM);
wherein the SDRAM includes a plurality of double data rate 2 (DDR2) SDRAM banks each of which has a 16-bit interface and is selected with a predetermined chip select signal, an upper data mask (UDQM) and a lower data mask (LDQM).
11 . The processor board of claim 10 , wherein the FPGA controls the plurality of DDR2 SDRAM banks and an electrical interface to the plurality of DDR2 SDRAM banks.
12 . The processor board of claim 11 , wherein the FPGA further comprises:
a technical standard balanced voltage digital interface circuit with up to 16 transmitters (TX) and up to 16 receivers (RX), and/or a plurality of low-voltage differential signaling (LVDS) Discrete Differential inputs/outputs (I.O) for use by the FPGA.
13 . The processor board of claim 1 , wherein the processor board includes a 3.3V supply voltage.
14 . The processor board of claim 13 , further comprising:
a plurality of synchronous buck regulators to generate secondary supply voltages for the FPGA and the processor.
15 . The processor board of claim 14 , further comprising:
an output termination voltage regulator to regulate power through a plurality of DDR2 SDRAM transmission lines and achieve power conservation by increasing/decreasing current so that an output termination voltage is half of the supply voltage.
16 . The processor board of claim 1 , further comprising:
a radiation tolerant oscillator which operates based off a single, on-board 50 MHz oscillator;
wherein the oscillator sources the processor and the FPGA; and
wherein SpaceWire clocks are generated by the processor and the FPGA, separately and internally.
17 . The processor board of claim 16 , wherein the FPGA is responsible for generating the data bus, the PCI interface, and an external memory clock for the processor.
18 . The processor board of claim 17 , wherein power-up sequencing after power-on is automatic to reduce in-rush current.
19 . The processor board of claim 18 , wherein the FPGA manages resets.