Electronic tampering detection

1 . In an electronic system on a circuit board having a processor and traces for distribution of power to circuit components on the board, a method of detecting tampering with the electronic system, comprising:

identifying a genuine impedance model of a power distribution network (PDN) electrically coupled to a circuit board by representing an impedance of the PDN as an RLC (Resistance, Inductance, Capacitance) circuit, further comprising:

identifying the genuine impedance model by gathering, by a logic element in electrical communication with voltage outputs of the PDN, samples of genuine impedance profiles from the PDN in a trusted environment; and

collecting the samples in an enrollment phase for successive comparison with a deviant impedance model gathered from a suspect environment;

storing the genuine impedance model as an indicator of normal operation of an electronic system on the circuit board;

determining a change to the impedance of the PDN based on a successive gathering of the impedance of the PDN to form the deviant impedance model from the circuit board; and

concluding, in the logic element, that a tampering event has occurred to the circuit board based on a comparison of a distance between a probability distribution of genuine impedance values from the genuine impedance model and tampered impedance values from the deviant impedance model.

2 . The method of claim 1 further comprising:

generating an expected impedance signature from the genuine impedance model based on a response of the PDN; and

determining the tampering event by computing a successive signature and identifying a difference between the successive signature and the expected impedance signature.

3 . The method of claim 1 further comprising generating, from the PDN, an equivalent RLC circuit, and identifying the genuine impedance model from the equivalent RLC circuit.

4 . The method of claim 3 further comprising identifying the genuine impedance model based on current flow characteristics measured at a range of frequencies exhibited by the PDN.

5 . The method of claim 3 further comprising:

deploying a logic element on the circuit board of an electronic system under test, the logic element including instructions for identifying the genuine impedance model, and

receiving inputs to the equivalent RLC circuit via electrical communication of the logic element with the PDN.

6 . The method of claim 5 wherein the logic element is a Field Programmable Gate Array (FPGA).

7 . The method of claim 1 further comprising:

generating the genuine impedance model by stimulating the PDN by drawing electrical current with different frequencies; and

measuring voltage drops resulting from the current draw at the different frequencies.

8 . The method of claim 1 wherein the logic element computes the distance from, for a plurality of frequencies, a non-zero covariance between a probability density function (PDF) of the genuine impedance model and the deviant impedance model.

9 . The method of claim 8 wherein the distance is based on a Wasserstein distance.

10 . In an electronic system on a circuit board having a processor and traces for distribution of power to circuit components on the board, a method of detecting tampering with the electronic system, comprising:

identifying a genuine impedance model of a power distribution network (PDN) on a circuit board by representing an impedance of the PDN as an RLC (Resistance, Inductance, Capacitance) circuit;

storing the genuine impedance model as an indicator of normal operation of an electronic system on the circuit board;

determining a change to the impedance of the PDN based on a successive gathering of the impedance of the PDN to form a deviant impedance model from the circuit board; and

concluding a tampering event has occurred to the circuit board based on a comparison of the genuine impedance model and the deviant impedance model;

further comprising comparing the genuine impedance model and the deviant impedance model based on a cumulative distribution function (CDF) of impedance based on respective models of trusted impedance and suspect impedance, further comprising a comparison of a distance between a probability distribution of genuine impedance values from the genuine impedance model and tampered impedance values from the deviant impedance model.

11 . A PCB board component device on a circuit board implementing an electronic system having a processor and traces for distribution of power to circuit components on the board for detecting tampering with the electronic system, comprising:

an on-board circuit defining a logic element in electrical communication with a power distribution network (PDN) on a circuit board;

a plurality of connections on the circuit board to a power distribution network (PDN) on the circuit board for identifying a genuine impedance model of the PDN by representing an impedance of the PDN as an RLC (Resistance, Inductance, Capacitance) circuit, further comprising gathered genuine samples of impedance profiles from the PDN in a trusted environment, the genuine samples collected in an enrollment phase for successive comparison with a deviant impedance model gathered from a suspect environment;

a memory for storing the genuine impedance model as an indicator of normal operation of an electronic system on the circuit board;

the circuit board configured for determining a change to the impedance model based on a successive gathering of the impedance of the PDN to form the deviant impedance model from the circuit board; and

the circuit board configured for concluding a tampering event has occurred to the circuit board based on a comparison of a distance between a probability distribution of genuine impedance values from the genuine impedance model and tampered impedance values from the deviant impedance model.

12 . The device of claim 11 further comprising:

an impedance signature generated from the genuine impedance model based on a response of the PDN; and

the processor further configured for determining an occurrence of the tampering event by computing a successive signature and identifying a difference between the successive signature and the expected impedance signature.

13 . The device of claim 11 further comprising an equivalent RLC circuit generated from the PDN, the genuine impedance model based on the equivalent RLC circuit.

14 . A computer program product comprising a non-transitory computer readable storage medium storing program code that, when executed by a processor, performs, in an electronic system on a circuit board having a processor and traces for distribution of power to circuit components on the board, a method of detecting tampering with the electronic system, the method comprising:

forming an on-board circuit defined by a logic element in electrical communication with a power distribution network (PDN) on a circuit board;

identifying a genuine impedance model of a the PDN on the circuit board by evaluating an impedance of the PDN as an RLC (Resistance, Inductance, Capacitance) circuit, further comprising

identifying the genuine impedance model by gathering genuine samples of impedance profiles from the PDN in a trusted environment; and

collecting the genuine samples in an enrollment phase for successive comparison with a deviant impedance model gathered from a suspect environment;

storing the genuine impedance model as an indicator of normal operation of an electronic system on the circuit board;

determining a change to the impedance of the PDN based on a successive gathering of the impedance of the PDN to form the deviant impedance model from the circuit board; and

concluding a tampering event has occurred to the circuit board based on a comparison of a distance between a probability distribution of genuine impedance values from the genuine impedance model and tampered impedance values from the deviant impedance model.