Semiconductor device and control method thereof

1 . A semiconductor device comprising:

a memory circuit configured to store pre-calculation data including at least one of plaintext and ciphertext;

an encryption processing circuit configured to perform crypt processing including encryption processing of the plaintext and decryption processing of the ciphertext;

a hash processing circuit including a buffer and configured to perform hash calculation processing to calculate a hash value;

a bus configured to connect the memory circuit, the encryption processing circuit, and the hash processing circuit to communicate with one another; and

an alternative connection path configured to connect the encryption processing circuit and the hash processing circuit to communicate with each other,

wherein the semiconductor device is configured to transfer, from the memory circuit to the encryption processing circuit, the pre-calculation data for each first calculation unit of the encryption processing circuit,

wherein the encryption processing circuit is configured to apply the crypt processing to the transferred pre-calculation data for the first calculation unit, generate post-calculation data for the first calculation unit, and transfer the generated post-calculation data for the first calculation unit to the hash processing circuit, the post-calculation data including at least one of the ciphertext and the plaintext,

wherein the hash processing circuit is configured to store the post-calculation data for the first calculation unit in the buffer, and apply the hash calculation processing to the post-calculation data for each second calculation unit of the hash processing circuit,

wherein the semiconductor device is configured to transfer the post-calculation data for the first calculation unit or the post-calculation data for the second calculation unit to the memory circuit,

wherein the crypt processing and the hash calculation process are performed in parallel,

wherein the crypt processing, the hash calculation process, and the transfer of the post-calculation data to the memory circuit are performed repeatedly multiple times,

wherein the hash processing circuit is configured to output, to the memory circuit, the hash value corresponding to the post-calculation data obtained by applying the crypt processing to the pre-calculation data,

wherein the semiconductor device is configured to switch a transfer mode between a first mode and a second mode,

wherein, in the first mode, the encryption processing circuit transfers the post-calculation data to the hash processing circuit only via the bus, and

wherein, in the second mode, the encryption processing circuit transfers the post-calculation data to the hash processing circuit via the bus and the alternative connection path.

2 . The semiconductor device according to claim 1 ,

wherein the semiconductor device is further configured to switch a hash processing mode between a third mode and a fourth mode,

wherein, in the third mode, the hash processing circuit applies the hash calculation processing to the post-calculation data received via the bus, and

wherein, in the fourth mode, the hash processing circuit applies the hash calculation processing to the post-calculation data received via the alternative connection path.

3 . The semiconductor device according to claim 2 ,

wherein the hash processing circuit includes a detecting circuit configured to detect a status of the buffer and output a waiting signal to the encryption processing circuit when the status indicates that the buffer is not capable of storing the post-calculation data, and

wherein the encryption processing circuit includes a controller circuit configured to, when the waiting signal is received, stop transferring the post-calculation data to at least one of the bus or the alternative connection path.

4 . The semiconductor device according to claim 1 ,

wherein the bus comprises a first and a second bus,

wherein the first bus is configured to transfer the pre-calculation data from the memory circuit to the encryption processing circuit, and

wherein the second bus is configured to transfer the post-calculation data from the encryption processing circuit to the memory circuit.

5 . The semiconductor device according to claim 1 ,

wherein the encryption processing circuit includes a plurality of bus ports configured to input the pre-calculation data and output the post-calculation data via the bus,

wherein the bus ports include a first bus port and a second bus port,

wherein the post-calculation data outputted via the first bus port are transferred to the memory circuit,

wherein the post-calculation data outputted via the second bus port are transferred to the hash processing circuit, and

wherein the hash processing circuit applies the hash calculation processing to the post-calculation data received via the second bus port and the bus.

6 . The semiconductor device according to claim 5 ,

wherein the semiconductor device is further configured to switch the transfer mode between a fifth mode and a sixth mode,

wherein, in the fifth mode, the encryption processing circuit transfers the post-calculation data only via either one of the first bus port or the second bus port, and

wherein, in the sixth mode, the encryption processing circuit transfers the post-calculation data via the first bus port and the second bus port.

7 . The semiconductor device according to claim 5 ,

wherein the bus comprises a first and a second bus,

wherein the first bus is configured to transfer the pre-calculation data from the memory circuit to the encryption processing circuit, and transfer the post-calculation data from the encryption processing circuit to the hash processing circuit, and

wherein the second bus is configured to transfer the post-calculation data from the encryption processing circuit to the memory circuit.

8 . The semiconductor device according to claim 1 , further comprises:

a transfer circuit configured to perform the transfer of the pre-calculation data and the post-calculation data; and

a control circuit configured to control the memory circuit, the encryption processing circuit and the hash processing circuit.

9 . A method for encryption processing, the method comprising:

(a) transferring pre-calculation data from a memory device to an encryption processing device for each first processing unit;

(b) generating post-calculation data for the first processing unit by performing an encryption process the pre-calculation data for the first processing unit;

(c) transferring the post-calculation data to a hash processing device;

(d) storing, in a buffer of the hash processing device, the post-calculation data for the first processing unit;

(e) generating a hash value by performing a hash processing on post-calculation data for a second processing unit stored in the buffer of the hash processing device;

(f) transferring the post-calculation data for the first processing unit or the post-calculation data for the second processing unit to the memory device;

(g) storing the hash value corresponding the post-calculation data,

wherein (b) and (e) are performed in parallel,

wherein (a), (b), (c), (d) and (e) are performed repeatedly multiple times,

wherein (c) is performed by outputting the post-calculation data of the first processing unit to a connection path configured to communicate from the encryption processing device to the hash processing device,

wherein (f) is performed by outputting the post-calculation data for the first processing unit to a bus configured to provide bidirectional communicate among the memory device, the encryption processing device, and the hash processing device,

wherein (e) is performed by applying the hash processing to the post-calculation data received via the connection path,

wherein the method further comprises (h) switching a transfer mode between a first mode and a second mode,

wherein, in the first mode, the encryption processing device transfers the post-calculation data the hash processing device only via the bus, and

wherein, in the second mode, the encryption processing device transfers the post-calculation data to the hash processing device via the bus and the connection path.

10 . The method according to claim 9 , further comprises:

(i) switching a hash processing mode between a third mode and a fourth mode,

wherein, in the third mode, the hash processing device applies the hash calculation process to the calculated post-calculation data received via the bus, and

wherein, in the fourth mode, the hash processing circuit applies the hash calculation process to the post-calculation data received via the connection path.

11 . The method according to claim 10 ,

wherein the hash processing device includes a detecting device configured to detect a status of the buffer and output a waiting signal to the encryption processing device when the status indicates that the buffer is not capable of storing the post-calculation data, and

wherein the encryption processing device includes a controller device configured to, when the waiting signal is received, stop transferring the post-calculation data to at least one of the bus or the connection path.

12 . The method according to claim 9 ,

wherein the bus comprises a first and a second bus,

wherein the first bus is configured to transfer the pre-calculation data from the memory device to the encryption processing device, and transfer the post-calculation data from the encryption processing device to the hash processing device, and

wherein the second bus is configured to transfer the post-calculation data from the encryption processing device to the memory device.

13 . The method according to claim 9 ,

wherein the encryption processing device includes a plurality of bus ports configured to input the pre-calculation data and output the post-calculation data with the bus,

wherein the bus ports include a first bus port and a second bus port,

wherein (f) is performed by transferring the post-calculation data outputted via the first bus port to the memory device,

wherein (c) is performed by transferring the post-calculation data outputted via the second bus port to the hash processing device, and

wherein (e) is performed by applying the hash calculation processing to the post-calculation data received via the second bus port and the bus.

14 . The method according to claim 13 ,

wherein the encryption processing device is configured to switch a transfer mode between a fifth mode and a sixth mode,

wherein, in the fifth mode, the encryption processing device transfers the post-calculation data only via either one of the first bus port or the second bus port, and

wherein, in the sixth mode, the encryption processing device transfers the post-calculation data via the first bus port and the second bus port.

15 . The method according to claim 13 ,

wherein the bus comprises a first and a second bus,

wherein the first bus is configured to transfer the pre-calculation data from the memory device to the encryption processing device, and transfer the post-calculation data from the encryption processing device to the hash processing device, and

wherein the second bus is configured to transfer the post-calculation data from the encryption processing device to the memory device.