Method for performing system task in unprivileged mode and associated electronic device

1 . An electronic device, comprising:

a processor, arranged to utilize an instruction set architecture (ISA) to transmit a first request with a first verification key to a hardware circuit, for requesting the hardware circuit to execute a system task in an unprivileged mode, wherein the ISA corresponds to the hardware circuit, the system task is associated with a privileged mode, and comprises operations of accessing a protected memory region; and when the processor is in the unprivileged mode, the processor is not capable of directly accessing the protected memory region; and

the hardware circuit, arranged to determine whether to execute the system task according to the first verification key, wherein the operations comprise requesting to access a target hardware address, and the target hardware address is associated with the protected memory region;

wherein in response to the processor being initially in the privileged mode, the processor transmits a second request to the hardware circuit for requesting the hardware circuit to generate a key; and the hardware circuit is further arranged to write the key into the target hardware address as a second verification key, and return the key to the processor as the first verification key;

wherein in response to the processor being returned from the unprivileged mode to the privileged mode, the processor requests the hardware circuit to regenerate the key.

2 . The electronic device of claim 1 , wherein the processor is initially in the privileged mode, and is further arranged to execute a plurality of user programs.

3 . The electronic device of claim 2 , wherein in response to the processor starting to execute the plurality of user programs, the processor is switched from the privileged mode to the unprivileged mode, and after a last user program of the plurality of user programs is executed, the processor is switched from the unprivileged mode to the privileged mode.

4 . The electronic device of claim 1 , wherein in response to the system task being executed in the unprivileged mode, the hardware circuit is further arranged to read the second verification key from the target hardware address, and compare the first verification key with the second verification key to generate a comparison result.

5 . The electronic device of claim 4 , wherein in response to the comparison result indicating that the first verification key matches the second verification key, the hardware circuit determines to access the target hardware address to generate an access result.

6 . The electronic device of claim 5 , wherein the hardware circuit transmits the access result and a success response to the processor.

7 . The electronic device of claim 4 , wherein in response to the comparison result indicating that the first verification key does not match the second verification key, the hardware circuit determines not to access the target hardware address.

8 . The electronic device of claim 7 , wherein the hardware circuit transmits a failure response to the processor.

9 . A method for executing a system task in an unprivileged mode, wherein the system task is associated with a privileged mode, and comprises operations of accessing a protected memory region; and the method comprises:

utilizing, by a processor, an instruction set architecture (ISA) to transmit a first request with a first verification key to a hardware circuit, for requesting the hardware circuit to execute the system task in the unprivileged mode, wherein the ISA corresponds to the hardware circuit; and when the processor is in the unprivileged mode, the processor is not capable of directly accessing the protected memory region; and

determining, by the hardware circuit, whether to execute the system task according to the first verification key, wherein the operations comprise requesting to access a target hardware address, and the target hardware address is associated with the protected memory region;

wherein the method further comprises:

in response to the processor being initially in the privileged mode, transmitting, by the processor, a second request to the hardware circuit for requesting the hardware circuit to generate a key;

writing, by the hardware circuit, the key into the target hardware address as a second verification key;

returning, by the hardware circuit, the key to the processor as the first verification key; and

in response to the processor being returned from the unprivileged mode to the privileged mode, requesting, by the processor, the hardware circuit to regenerate the key.

10 . The method of claim 9 , wherein the processor is initially in the privileged mode, and the method further comprises:

executing, by the processor, a plurality of user programs.

11 . The method of claim 10 , wherein the step of executing, by the processor, the plurality of user programs comprises:

in response to the processor starting to execute the plurality of user programs, switching the processor from the privileged mode to the unprivileged mode; and

after a last user program of the plurality of user programs is executed, switching the processor from the unprivileged mode to the privileged mode.

12 . The method of claim 9 , further comprising:

in response to the system task being executed in the unprivileged mode, reading, by the hardware circuit, the second verification key from the target hardware address; and

comparing, by the hardware circuit, the first verification key with the second verification key to generate a comparison result.

13 . The method of claim 12 , wherein the step of comparing, by the hardware circuit, the first verification key with the second verification key to generate the comparison result comprises:

in response to the comparison result indicating that the first verification key matches the second verification key, determining, by the hardware circuit, to access the target hardware address to generate an access result.

14 . The method of claim 13 , wherein the step of determining, by the hardware circuit, to access the target hardware address to generate the access result comprises:

transmitting, by the hardware circuit, the access result and a success response to the processor.

15 . The method of claim 12 , wherein the step of comparing, by the hardware circuit, the first verification key with the second verification key to generate the comparison result comprises:

in response to the comparison result indicating that the first verification key does not match the second verification key, determining, by the hardware circuit, not to access the target hardware address.

16 . The method of claim 15 , wherein the step of determining, by the hardware circuit, not to access the target hardware address comprises:

transmitting, by the hardware circuit, a failure response to the processor.