Optimization of circuit design layout using dynamic probability of success of component placement in integrated circuit design

1 . A method for performing placement of cells in a circuit design layout, the method comprising:

placing the cells at candidate locations in the circuit design layout in accordance with design rules;

determining, by a processing device, for each location of the candidate locations, a probability of design rule success for the placement of each cell of the cells based on one or more of available candidate locations;

predicting a first updated probability of design rule success for placement of a first additional cell at the candidate locations;

predicting a second updated probability of design rule success for placement of a second additional cell at additional candidate locations in the circuit design layout that are different from the candidate locations; and

updating a library data structure to include the first updated and the second updated probabilities of design rule success of the placement of the first additional cell at the candidate locations and the second additional cell at the additional candidate location.

2 . The method of claim 1 , further comprising determining a final location, of the candidate locations, for each cell of the cells in dependence on the first updated and the second updated probabilities probability of design rule success.

3 . The method of claim 1 , further comprising removing a candidate location, of the candidate locations, in dependence on the first updated and the second updated probabilities of design rule success.

4 . The method of claim 1 , wherein one of the cells is placed without determining a probability of design rule success for all cells of the circuit design layout according to the design rules.

5 . The method of claim 1 , further including performing optimization of the placement of the cells based on the probability of design rule success for the placement of each cell.

6 . The method of claim 5 , further comprising performing optimization based on one or more of inserting an additional cell and sizing a cell of the cells.

7 . The method of claim 6 , further comprising determining an optimization metric based on the optimization.

8 . The method of claim 7 , further comprising updating a probability of design rule success of at least one cell based on the optimization metric.

9 . The method of claim 8 , further comprising storing the updated probability of design rule success in the library data structure.

10 . The method of claim 8 , further comprising placing another additional cell at a remaining candidate location in dependence on the stored probability of design rule success of the at least one cell within the library data structure.

11 . The method of claim 1 , further comprising:

determining, for each respective location of the candidate locations, a neighboring probability of design rule success for placement of a neighboring cell that neighbors the respective location; and

determining a final location, of the candidate locations, for the first additional cell in dependence on (i) the first updated probability of design rule success for placement of the first additional cell at the respective locations and (ii) the determined neighboring probabilities of design rule success for placement of success of the neighboring cells neighboring the respective locations.

12 . The method of claim 11 , wherein a neighboring cell is a cell that is, at least, one of the cells that is within a threshold area adjacent to a respective location of the candidate locations.

13 . The method of claim 1 , wherein at least one of the design rules includes one or more of:

a complexity of one or more of a metal geometry and a base layer geometry of cells in the circuit design layout;

an area constraint;

a floorplan constraint; and

a complexity level of neighboring cells located in a threshold area adjacent to a location of a particular cell.

14 . A system for performing placement of cells in a circuit design layout, the system comprising:

a memory storing instructions; and

a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:

place the cells at candidate locations in the circuit design layout in accordance with design rules;

determine, for each location of the candidate locations, a probability of design rule success for the placement of each cell of the cells based on one or more of available candidate locations;

determine an optimization metric and a probability of design rule success of locating a first additional cell in a given location of the candidate locations;

determine an optimization metric and a probability of design rule success of locating a second additional cell in the given location; and

select the first additional cell to be located at the given location based on the optimization metrics and the probabilities of design rule success of the first additional cell and the second additional cell.

15 . The system of claim 14 , wherein the processor stores, in the memory, a library data structure including probability values of success for each candidate location of the candidate locations based on the determined probability of design rule success of the placement of the first additional cell at the candidate locations.

16 . The system of claim 15 , wherein the processor:

places the second additional cell at a remaining candidate location in dependence on the stored probability values of success.

17 . The system of claim 14 , wherein the processor:

determines an optimization metric and a probability of design rule success of locating a first additional cell in a given location of the candidate locations;

determines an optimization metric and a probability of design rule success of locating a second additional cell in the given location, wherein the optimization metric of locating the second additional cell at the given location is greater than the optimization metric of locating the first additional cell at the given location and wherein the probability of design rule success of locating the second additional cell in the given location is less than the probability of design rule success of locating the first additional cell in the given location; and

selects the first additional cell to be located at the given location in dependence on the determined optimization metrics and the probabilities of design rule success of the first additional cell and the second additional cell.

18 . A non-transitory computer readable medium comprising stored instructions for placement of cells in a circuit design layout, the instructions when executed by a processor, cause the processor to:

determine a probability of design rule success for placement of initial cells in dependence on a cell library for a plurality of cells and first design rules for the plurality of cells;

retrieve second design rules for placement of a first additional cell, of the plurality of cells, within the circuit design layout;

place the first additional cell at available candidate locations in the circuit design layout in accordance with the second design rules; and

determine, for each location of the candidate locations, a probability of design rule success with respect to the second design rules for the placement of the first additional cell.

19 . The non-transitory computer readable medium of claim 18 , wherein the second rules includes one or more of:

a complexity of one or more of a metal geometry and a base layer geometry of cells in the circuit design layout;

an area constraint;

a floorplan constraint; and

a complexity level of neighboring cells located in a threshold area adjacent to a location of a particular cell.