Identifying circuit elements and/or ports for threat analysis and risk assessment

1 . A method, comprising:

receiving a first set of one or more ports and circuit elements in a circuit design, wherein the first set of one or more ports and circuit elements is expected to cause damage if the first set of one or more ports and circuit elements is compromised, and wherein compromising a first port in the first set of one or more ports and circuit elements allows exploitation of the first port by a user;

determining a second set of one or more ports and circuit elements in the circuit design by performing one or more of (1) forward path tracing from the first set of one or more ports and circuit elements and (2) backward path tracing from the first set of one or more ports and circuit elements; and

generating, by a processor, a report based on the second set of one or more ports and circuit elements in the circuit design, wherein the report identifies one or more of threat scenarios and damage scenarios in the circuit design.

2 . The method of claim 1 , wherein the circuit design has multiple modes, wherein different portions of the circuit design are activated in each mode, and wherein for each mode, the one or more of (1) the forward path tracing from the first set of one or more ports and circuit elements and (2) the backward path tracing from the first set of one or more ports and circuit elements is performed only on the activated portions of the circuit design.

3 . The method of claim 2 , wherein the report includes multiple sections, and wherein each section corresponds to a mode.

4 . The method of claim 1 , further comprising computing observability probabilities associated with the second set of one or more ports and circuit elements, and wherein the report includes the observability probabilities.

5 . The method of claim 4 , wherein the report ranks the second set of one or more ports and circuit elements based on the observability probabilities.

6 . The method of claim 4 , wherein the report includes a subset of the second set of one or more ports and circuit elements which have observability probabilities that are greater than a threshold observability probability.

7 . The method of claim 4 , further comprising adding threat detection circuitry for a subset of the second set of one or more ports and circuit elements which have observability probabilities that are greater than a threshold observability probability.

8 . A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

receive a first set of one or more ports and circuit elements in a circuit design, wherein the first set of one or more ports and circuit elements is expected to cause damage if the first set of one or more ports and circuit elements is compromised, and wherein compromising a first port in the first set of one or more ports and circuit elements allows exploitation of the first port by a user;

determine a second set of one or more ports and circuit elements in the circuit design by performing one or more of (1) forward path tracing from the first set of one or more ports and circuit elements and (2) backward path tracing from the first set of one or more ports and circuit elements; and

generate a report based on the second set of one or more ports and circuit elements in the circuit design, wherein the report identifies one or more of threat scenarios and damage scenarios in the circuit design.

9 . The non-transitory computer-readable medium of claim 8 , wherein the circuit design has multiple modes, wherein different portions of the circuit design are activated in each mode, and wherein for each mode, the one or more of (1) the forward path tracing from the first set of one or more ports and circuit elements and (2) the backward path tracing from the first set of one or more ports and circuit elements is performed only on activated portions of the circuit design.

10 . The non-transitory computer-readable medium of claim 9 , wherein the report includes multiple sections, and wherein each section corresponds to a mode.

11 . The non-transitory computer-readable medium of claim 8 , wherein the stored instructions, which when executed by the processor, cause the processor to compute observability probabilities associated with the second set of one or more ports and circuit elements, and wherein the report includes the observability probabilities.

12 . The non-transitory computer-readable medium of claim 11 , wherein the report ranks the second set of one or more ports and circuit elements based on the observability probabilities.

13 . The non-transitory computer-readable medium of claim 11 , wherein the report includes a subset of the second set of one or more ports and circuit elements which have observability probabilities that are greater than a threshold observability probability.

14 . The non-transitory computer-readable medium of claim 11 , wherein the stored instructions, which when executed by the processor, cause the processor to add threat detection circuitry for a subset of the second set of one or more ports and circuit elements which have observability probabilities that are greater than a threshold observability probability.

15 . An apparatus, comprising:

a memory storing instructions; and

a processor, coupled with the memory and to execute the instructions, the instructions when executed causing the processor to:

receive a first set of one or more ports and circuit elements in a circuit design, wherein the first set of one or more ports and circuit elements is expected to cause damage if the first set of one or more ports and circuit elements is compromised, and wherein compromising a first port in the first set of one or more ports and circuit elements a lows exp Joi of the first port by a user;

determine a second set of one or more ports and circuit elements in the circuit design by performing one or more of (1) forward path tracing from the first set of one or more ports and circuit elements and (2) backward path tracing from the first set of one or more ports and circuit elements;

compute observability probabilities associated with the second set of one or more ports and circuit elements; and

generate a report based on the second set of one or more ports and circuit elements in the circuit design, wherein the report includes the observability probabilities, and wherein the report is used for performing threat analysis and risk assessment for the circuit design.

16 . The apparatus of claim 15 , wherein the circuit design has multiple modes, wherein different portions of the circuit design are activated in each mode, and wherein for each mode, the one or more of (1) the forward path tracing from the first set of one or more ports and circuit elements and (2) backward path tracing from the first set of one or more ports and circuit elements is performed only on activated portions of the circuit design.

17 . The apparatus of claim 16 , wherein the report includes multiple sections, and wherein each section corresponds to a mode.

18 . The apparatus of claim 15 , wherein the report ranks the second set of one or more ports and circuit elements based on the observability probabilities.

19 . The apparatus of claim 15 , wherein the report includes a subset of the second set of one or more ports and circuit elements which have observability probabilities that are greater than a threshold observability probability.

20 . The apparatus of claim 15 , wherein the stored instructions, which when executed by the processor, cause the processor to add threat detection circuitry for a subset of the second set of one or more ports and circuit elements which have observability probabilities that are greater than a threshold observability probability.