Sliced graphics processing unit (GPU) architecture in processor-based devices

1 . A processor-based device, comprising:

a graphics processing unit (GPU) comprising:

a plurality of hardware slices, each comprising a low-resolution Z buffer (LRZ);

a command processor (CP) circuit; and

an unslice primitive controller (PC_US);

the CP circuit configured to:

receive a graphics instruction from a central processing unit (CPU);

determine a graphics workload based on the graphics instruction; and

transmit the graphics workload to the PC_US;

the PC_US configured to:

receive the graphics workload from the CP circuit;

partition the graphics workload into a plurality of subbatches; and

distribute each subbatch of the plurality of subbatches to a slice primitive controller (PC_S) of a hardware slice of the plurality of hardware slices for processing;

wherein each LRZ is configured to store cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices by being configured to, for each hardware slice:

map screen coordinates into a slice space that is continuous in coordinates and holds blocks for the hardware slice only; and

address tiles based on coordinates in the slice space.

2 . The processor-based device of claim 1 , wherein each hardware slice of the plurality of hardware slices further comprises a plurality of slice hardware units, the plurality of slice hardware units comprising a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a render backend (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader/texture pipe (FS/TP), and a cluster cache (CCHE).

3 . The processor-based device of claim 2 , wherein:

the GPU further comprises a unified cache (UCHE) communicatively coupled to each CCHE of each hardware slice of the plurality of hardware slices; and

each CCHE of each hardware slice of the plurality of hardware slices and the UCHE are configured to operate as hierarchical caches.

4 . The processor-based device of claim 3 , wherein:

each CCHE of each hardware slice of the plurality of hardware slices is configured to:

receive data from one or more clients comprising one or more of the plurality of slice hardware units of the hardware slice; and

synchronize the one or more clients; and

the UCHE is configured to synchronize the plurality of hardware slices.

5 . The processor-based device of claim 2 , wherein:

the GPU further comprises an unslice vertex parameter cache (VPC_US);

the plurality of slice hardware units of each hardware slice of the plurality of hardware slices further comprises:

a slice Triangle Setup Engine front end (TSEFE_S);

a slice vertex parameter cache front end (VPCFE_S); and

a slice vertex parameter cache back end (VPCBE_S);

each VPCFE_S is configured to:

receive, from the VS of the corresponding hardware slice, primitive attribute and position outputs generated by the VS; and

write the primitive attribute and position outputs to the GMEM of the corresponding hardware slice;

each TSEFE_S is configured to:

determine triangle visibility for each of one or more hardware slices of the plurality of hardware slices, based on the primitive attributes and position outputs; and

transmit, to the VPC_US, a corresponding one or more indications of triangle visibility for each of the one or more hardware slices;

the VPC_US is configured to:

receive the one or more indications of triangle visibility; and

assign, based on the one or more indications of triangle visibility, triangles visible to each of the one or more hardware slices to the corresponding hardware slice; and

each VPCBE_S is configured to:

based on the triangles assigned by the VPC_US of the corresponding hardware slice, fetch vertices for the triangles visible to the corresponding hardware slice; and

transmit the vertices to a Triangle Setup Engine (TSE) of the corresponding hardware slice.

6 . The processor-based device of claim 1 , wherein the PC_US is configured to distribute each subbatch by being configured to:

determine, for the plurality of hardware slices, a corresponding plurality of current processing utilizations; and

distribute each subbatch of the plurality of subbatches based on the plurality of current processing utilizations.

7 . The processor-based device of claim 1 , wherein a size of each subbatch of the plurality of subbatches is configurable.

8 . The processor-based device of claim 1 , wherein each subbatch comprises 256 primitives.

9 . The processor-based device of claim 1 , wherein the PC_US is configured to distribute each subbatch based on a round-robin slice selection mechanism.

10 . A processor-based device, comprising:

means for receiving a graphics instruction from a central processing unit (CPU);

means for determining a graphics workload based on the graphics instruction;

means for partitioning the graphics workload into a plurality of subbatches; and

means for distributing each subbatch of the plurality of subbatches to a hardware slice of a plurality of hardware slices of a graphical processing unit (GPU) for processing;

wherein each hardware slice of the plurality of hardware slices comprises means for storing cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices, the means for storing cache lines comprising:

means for mapping screen coordinates into a slice space that is continuous in coordinates and holds blocks for the hardware slice only; and

means for addressing tiles based on coordinates in the slice space.

11 . A method for operating a graphics processing unit (GPU) comprising a plurality of hardware slices, each comprising a low-resolution Z buffer (LRZ), the method comprising:

receiving, by a command processor (CP) circuit of a graphics processing unit (GPU), a graphics instruction from a central processing unit (CPU);

determining a graphics workload based on the graphics instruction;

transmitting the graphics workload to an unslice primitive controller (PC_US) of the GPU;

receiving, by the PC_US, the graphics workload from the CP circuit;

partitioning the graphics workload into a plurality of subbatches;

distributing each subbatch of the plurality of subbatches to a slice primitive controller (PC_S) of a hardware slice of the plurality of hardware slices of the GPU for processing; and

storing, by each LRZ of each hardware slice of the plurality of hardware slices, cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices;

wherein storing cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices comprises:

mapping screen coordinates into a slice space that is continuous in coordinates and holds blocks for the hardware slice only; and

addressing tiles based on coordinates in the slice space.

12 . The method of claim 11 , wherein each hardware slice of the plurality of hardware slices further comprises a plurality of slice hardware units, the plurality of slice hardware units comprising a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a render backend (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader/texture pipe (FS/TP), and a cluster cache (CCHE).

13 . The method of claim 12 , wherein:

the GPU further comprises a unified cache (UCHE) communicatively coupled to each CCHE of each hardware slice of the plurality of hardware slices;

each CCHE of each hardware slice of the plurality of hardware slices and the UCHE are configured to operate as hierarchical caches; and

the method further comprises:

receiving, by each CCHE of each hardware slice of the plurality of hardware slices, data from one or more clients comprising one or more of the plurality of slice hardware units of the hardware slice;

synchronizing, by each CCHE of each hardware slice of the plurality of hardware slices, the one or more clients; and

synchronizing, by the UCHE, the plurality of hardware slices.

14 . The method of claim 12 , wherein:

the GPU further comprises an unslice vertex parameter cache (VPC_US);

the plurality of slice hardware units of each hardware slice of the plurality of hardware slices further comprises:

a slice Triangle Setup Engine front end (TSEFE_S);

a slice vertex parameter cache front end (VPCFE_S); and

a slice vertex parameter cache back end (VPCBE_S); and

the method further comprises:

receiving, by each VPCFE_S from the VS of the corresponding hardware slice, primitive attribute and position outputs generated by the VS;

writing, by each VPCFE_S, the primitive attribute and position outputs to the GMEM of the corresponding hardware slice;

determining, by each TSEFE_S, triangle visibility for each of one or more hardware slices of the plurality of hardware slices, based on the primitive attributes and position outputs;

transmitting, by each TSEFE_S to the VPC_US, a corresponding one or more indications of triangle visibility for each of the one or more hardware slices;

receiving, by the VPC_US, the one or more indications of triangle visibility;

assigning, by the VPC_US based on the one or more indications of triangle visibility, triangles visible to each of the one or more hardware slices to the corresponding hardware slice;

based on the triangles assigned by the VPC_US of the corresponding hardware slice, fetching, by each VPCBE_S of each hardware slice of the plurality of hardware slices, vertices for the triangles visible to the corresponding hardware slice; and

transmitting the vertices to a Triangle Setup Engine (TSE) of the corresponding hardware slice.

15 . The method of claim 11 , wherein each subbatch comprises 256 primitives.

16 . The method of claim 11 , wherein distributing each subbatch is based on a round-robin slice selection mechanism.

17 . The method of claim 11 , wherein distributing each subbatch comprises:

determining, for the plurality of hardware slices, a corresponding plurality of current processing utilizations; and

distributing each subbatch of the plurality of subbatches based on the plurality of current processing utilizations.

18 . The method of claim 11 , wherein a size of each subbatch of the plurality of subbatches is configurable.

19 . A non-transitory computer-readable medium having stored thereon computer-executable instructions which, when executed by a processor, cause the processor to:

receive a graphics instruction;

determine a graphics workload based on the graphics instruction;

partition the graphics workload into a plurality of subbatches; and

distribute each subbatch of the plurality of subbatches to a slice primitive controller (PC_S) of a hardware slice of a plurality of hardware slices for processing;

wherein each hardware slice of the plurality of hardware slices comprises a low-resolution Z buffer (LRZ); and

the computer-executable instructions further cause the processor to store cache lines corresponding only to pixel tiles assigned to the corresponding hardware slice of the plurality of hardware slices by causing the processor to:

map screen coordinates into a slice space that is continuous in coordinates and holds blocks for the hardware slice only; and

address tiles based on coordinates in the slice space.

20 . The non-transitory computer-readable medium of claim 19 , wherein the computer-executable instructions cause the processor to distribute each subbatch based on a round-robin slice selection mechanism.

21 . The non-transitory computer-readable medium of claim 19 , wherein the computer-executable instructions cause the processor to distribute each subbatch by causing the processor to:

determine, for the plurality of hardware slices, a corresponding plurality of current processing utilizations; and

distribute each subbatch of the plurality of subbatches based on the plurality of current processing utilizations.

22 . The non-transitory computer-readable medium of claim 19 , wherein a size of each subbatch of the plurality of subbatches is configurable.

23 . The non-transitory computer-readable medium of claim 19 , wherein each subbatch comprises 256 primitives.

24 . The non-transitory computer-readable medium of claim 19 , wherein each hardware slice of the plurality of hardware slices comprises a plurality of slice hardware units, the plurality of slice hardware units comprising a geometry pipeline controller (GPC), a vertex shader (VS), a graphics rasterizer (GRAS), a render backend (RB), a cache and compression unit (CCU), a graphics memory (GMEM), a high-level sequencer (HLSQ), a fragment shader/texture pipe (FS/TP), and a cluster cache (CCHE).

25 . The non-transitory computer-readable medium of claim 24 , wherein the computer-executable instructions further cause the processor to:

receive data from one or more clients comprising one or more of the plurality of slice hardware units of the hardware slice;

synchronize the one or more clients; and

synchronize the plurality of hardware slices.

26 . The non-transitory computer-readable medium of claim 24 , wherein the computer-executable instructions further cause the processor to:

receive primitive attribute and position outputs generated by the VS of each hardware slice;

write the primitive attribute and position outputs to the GMEM of the hardware slice;

determine triangle visibility for each of one or more hardware slices of the plurality of hardware slices, based on the primitive attributes and position outputs;

assigning, based on a corresponding one or more indications of triangle visibility, triangles visible to each of the one or more hardware slices to the corresponding hardware slice;

fetch vertices for the triangles visible to the corresponding hardware slice; and

transmit the vertices to a Triangle Setup Engine (TSE) of the corresponding hardware slice.