Emission driver, gate driver, and display device
An emission driver includes emission stages including an input circuit; an inversion control circuit; an emission output circuit; a carry output circuit; and a boosting circuit. The boosting circuit includes a first transistor including a gate electrode connected to the control node, a first electrode configured to receive a next emission carry signal, and a second electrode connected to a boosting node, and a first capacitor including a first electrode connected to the control node and a second electrode connected to the boosting node.
1 . An emission driver comprising:
a plurality of emission stages, wherein
each of the emission stages includes:
an input circuit configured to provide an input signal to a control node based on a first clock signal;
an inversion control circuit configured to control a voltage of an inversion control node based on the first clock signal and a voltage of the control node;
an emission output circuit configured to output a high gate voltage as an emission signal based on the voltage of the control node and output a first low gate voltage as the emission signal based on the voltage of the inversion control node;
a carry output circuit configured to output the high gate voltage as an emission carry signal based on the voltage of the control node and output a second low gate voltage lower than the first low gate voltage as the emission carry signal based on the voltage of the inversion control node; and
a boosting circuit configured to boost the voltage of the control node, and the boosting circuit includes:
a first transistor (T5) including a gate electrode connected to the control node, a first electrode configured to receive a next emission carry signal, and a second electrode connected to a boosting node; and
a first capacitor including a first electrode connected to the control node and a second electrode connected to the boosting node.
2 . The emission driver of claim 1 , wherein
the first clock signal has alternating high level voltage and low level voltage, and
a difference between the high level voltage and the low level voltage is smaller than a difference between the high gate voltage and the second low gate voltage.
3 . The emission driver of claim 2 , wherein the high level voltage is smaller than the high gate voltage.
4 . The emission driver of claim 1 , wherein all transistors included in each of the emission stages are N-type transistors.
5 . The emission driver of claim 1 , wherein the input circuit includes a second transistor (T1) including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the control node.
6 . The emission driver of claim 1 , wherein the inversion control circuit includes a third transistor (T4) including a gate electrode connected to the control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the inversion control node.
7 . The emission driver of claim 6 , wherein the inversion control circuit further includes:
a fourth transistor (T7) including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the high gate voltage, and a second electrode;
a fifth transistor (T8) including a gate electrode connected to the control node, a first electrode configured to receive the first clock signal, and a second electrode connected to the second electrode of the fourth transistor (T7);
a sixth transistor (T9) including a gate electrode configured to receive the high gate voltage, a first electrode connected to the second electrode of the fourth transistor (T7), and a second electrode;
a seventh transistor (T10) including a gate electrode connected to the second electrode of the fourth transistor (T9), a first electrode configured to receive a second clock signal, and a second electrode;
an eighth transistor (T11) including a gate electrode connected to the second electrode of the seventh transistor (T10), a first electrode configured to receive the high gate voltage, and a second electrode connected to the inversion control node; and
a third capacitor including a first electrode connected to the gate electrode of the seventh transistor (T10), and a second electrode connected to the gate electrode of the eighth transistor (T11).
8 . The emission driver of claim 1 , wherein the emission output circuit includes:
a nineth transistor (T12) including a gate electrode connected to the control node, a first electrode configured to receive the high gate voltage, and a second electrode connected to an emission output node at which the emission signal is output;
a tenth transistor (T14) including a gate electrode connected to the inversion control node, a first electrode configured to receive the first low gate voltage, and a second electrode connected to the emission output node;
a fourth capacitor including a first electrode connected to the control node and a second electrode connected to the emission output node; and
a fifth capacitor including a first electrode connected to the inversion control node and a second electrode configured to receive the first low gate voltage.
9 . The emission driver of claim 1 , wherein the carry output circuit includes:
an eleventh transistor (T6) including a gate electrode connected to the control node, a first electrode configured to receive the high gate voltage, and a second electrode connected to a carry output node at which the emission carry signal is output; and
a twelfth transistor (T13) including a gate electrode connected to the inversion control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the carry output node.
10 . The emission driver of claim 1 , wherein each of the emission stages further includes a control circuit configured to control the voltage of the control node based on the voltage of the inversion control node.
11 . The emission driver of claim 10 , wherein the control circuit includes a thirteenth transistor (T2) including a gate electrode connected to the inversion control node, a first electrode configured to receive the second low gate voltage, and a second electrode connected to the control node.
12 . The emission driver of claim 1 , wherein
the control node includes a first control node and a second control node, and
each of the emission stages further includes a fourteenth transistor (T3) including a gate electrode configured to receive the high gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.
13 . The emission driver of claim 1 , wherein each of the emission stages further includes a fifteenth transistor (T16) including a gate electrode configured to receive a reset signal, a first electrode configured to receive the first low gate voltage, and a second electrode connected to the control node.
14 . A display device comprising:
a display panel including a plurality of pixels;
an emission driver including a plurality of emission stages configured to provide emission signals to the pixels; and
a driving controller configured to control the emission driver, wherein
each of the emission stages further includes:
an input circuit configured to provide an input signal to a control node based on a first clock signal;
an inversion control circuit configured to control a voltage of an inversion control node based on the first clock signal and a voltage of the control node;
an emission output circuit configured to output a high gate voltage as an emission signal based on the voltage of the control node and output a first low gate voltage as the emission signal based on the voltage of the inversion control node;
a carry output circuit configured to output the high gate voltage as an emission carry signal based on the voltage of the control node and output a second low gate voltage lower than the first low gate voltage as the emission carry signal based on the voltage of the inversion control node; and
a boosting circuit configured to boost the voltage of the control node, and the boosting circuit includes:
a first transistor (T5) including a gate electrode connected to the control node, a first electrode configured to receive a next carry signal, and a second electrode connected to a boosting node; and
a first capacitor including a first electrode connected to the control node and a second electrode connected to the boosting node.
15 . The display device of claim 14 , wherein
the first clock signal has alternating high level voltage and low level voltage, and
a difference between the high level voltage and the low level voltage is smaller than a difference between the high gate voltage and the second low gate voltage.