IP Library Granted Patent US 12682812
Granted Patent B2
US 12682812 · App. 19/008,658 · Granted Jul 14, 2026

Method of controlling display driver total charging time length of sub-pixels to improve bright-dark line issues

Inventors: Hsuan-Sheng Yang (Hsinchu City, TW); Ching-Wen Hou (Hsinchu City, TW); Yu-Ren Chiu (Taoyuan City, TW); Chi-Ming Lo (Hsinchu County, TW)
Assignee: NOVATEK Microelectronics Corp.
G09G3/2074G09G2300/0852G09G2310/0275G09G2310/06G09G2310/08
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Quick Facts
Patent No.
US 12682812
App. No.
19/008,658
Granted
Jul 14, 2026
Kind
B2
Abstract

A control method includes following operations: outputting a first control signal to a first switch coupled to a first sub-pixel of a display panel; outputting a second control signal to a second switch coupled to a second sub-pixel of the display panel; and outputting a driving voltage of display data according to a data output enable signal. The data output enable signal has a plurality of pulses, and a first time interval between a first pulse of the plurality of pulses and a second pulse of the plurality of pulses is shorter than a second time interval between the second pulse of the plurality of pulses and a third pulse of the plurality of pulses.

Claims (27)

1 . A control method of a display driver, comprising:

outputting a first control signal to a first switch coupled to a first sub-pixel of a display panel;

outputting a second control signal to a second switch coupled to a second sub-pixel of the display panel; and

outputting a driving voltage of a display data according to a data output enable signal, wherein the data output enable signal is configured to control an output switch which is comprised in a source driver and coupled to the first switch and the second switch,

wherein the data output enable signal comprises a plurality of pulses, and a first time interval between a first pulse of the plurality of pulses and a second pulse of the plurality of pulses is shorter than a second time interval between the second pulse of the plurality of pulses and a third pulse of the plurality of pulses,

wherein a rising edge of the second pulse is aligned with a falling edge of the first control signal.

2 . The control method of the display driver of claim 1 , wherein a falling edge of the second pulse is aligned with a rising edge of the second control signal.

3 . The control method of the display driver of claim 1 , wherein a delay time interval between the falling edge of the first control signal and a rising edge of the second control signal is shorter than the first time interval.

4 . The control method of the display driver of claim 1 , wherein each of the first pulse and the second pulse has a same pulse width.

5 . The control method of the display driver of claim 1 , wherein the first switch is turned on by the first control signal during the first time interval, and the second switch is turned on by the second control signal during the second time interval.

6 . The control method of the display driver of claim 1 , further comprising:

outputting a gate line signal to a third switch coupled between the first switch and the first sub-pixel; and

outputting the gate line signal to a fourth switch coupled between the second switch and the second sub-pixel.

7 . The control method of the display driver of claim 6 , wherein the second pulse is before a middle time point of an enable time interval of the gate line signal.

8 . The control method of the display driver of claim 6 , wherein a starting time point of the second time interval is before a middle time point of an enable time interval of the gate line signal.

9 . A control method of a display driver, comprising:

outputting a first control signal to a first switch coupled to a first sub-pixel of a display panel;

outputting a second control signal to a second switch coupled to a second sub-pixel of the display panel; and

outputting a driving voltage of a display data, wherein the driving voltage is outputted through the first switch and the second switch to the first sub-pixel and the second sub-pixel, wherein the driving voltage comprises a first driving voltage and a second driving voltage, and the display data comprises a first display data and a second display data,

wherein a first period of the first driving voltage of the first display data is shorter than a second period of the second driving voltage of the second display data,

wherein the first period equals to a first sum of a first pulse width of the first control signal and a second pulse width of a data output enable signal.

10 . The control method of the display driver of claim 9 , wherein the second period equals to a second sum of a third pulse width of the second control signal and the second pulse width of the data output enable signal.

11 . The control method of the display driver of claim 9 , further comprising:

outputting a gate line signal to a third switch coupled between the first switch and the first sub-pixel; and

outputting the gate line signal to a fourth switch coupled between the second switch and the second sub-pixel.

12 . The control method of the display driver of claim 11 , wherein a starting time point of the second period is before a middle time point of an enable time interval of the gate line signal.

13 . The control method of the display driver of claim 11 , wherein a rising edge of the second control signal is before a middle time point of an enable time interval of the gate line signal.