Scan driving circuit and display panel

Inventors: Ying-Hsiang Tseng (Shanghai, CN); Lina Xiao (Shanghai, CN); Qi Wang (Shanghai, CN); Jie Liu (Shanghai, CN)

Assignee: Everdisplay Optronics (Shanghai) Co., Ltd.

G09G3/2092 G11C19/184 G11C19/188 G09G2310/0286 G09G2310/067 G09G2310/08

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Quick Facts

Patent No.: US 12682817
App. No.: 18/709,827
Granted: Jul 14, 2026
Kind: B2

External Links

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Abstract

The present disclosure relates to the field of display panels and provides a scan driving circuit and a display panel. The scan driving circuit includes multiple stages of shift register units and a timing controller. Each stage of shift register unit includes 10 or 11 transistors and 2 capacitors. The timing controller includes three timing control signal lines.

Claims (46)

1 . A scan driving circuit, comprising multiple stages of shift register units, wherein each of the shift register units comprises:

a first transistor, wherein a first electrode of the first transistor is connected to a third node, a second electrode of the first transistor is connected to a signal input terminal, and a gate electrode of the first transistor is connected to a third timing control terminal;

a second transistor, wherein a first electrode of the second transistor is connected to a first power supply, a second electrode of the second transistor is connected to the third node, and a gate electrode of the second transistor is connected to a first timing control terminal;

a third transistor, wherein a first electrode of the third transistor is connected to the third timing control terminal, a second electrode of the third transistor is connected to a first node, and a gate electrode of the third transistor is connected to the third node;

a fourth transistor, wherein a first electrode of the fourth transistor is connected to the third node, a second electrode of the fourth transistor is connected to a second node, and a gate electrode of the fourth transistor is connected to a second power supply;

a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first power supply, and a gate electrode of the fifth transistor is connected to a second timing control terminal;

a sixth transistor, wherein a first electrode of the sixth transistor is connected to the second electrode of the fifth transistor, a second electrode of the sixth transistor is connected to the second node, and a gate electrode of the sixth transistor is connected to the first node;

a seventh transistor, wherein a second electrode of the seventh transistor is connected to the second power supply, and a gate electrode of the seventh transistor is connected to the first timing control terminal;

an eighth transistor, wherein a first electrode of the eighth transistor is connected to the first node, a second electrode of the eighth transistor is connected to the second power supply, and a gate electrode of the eighth transistor is connected to the third timing control terminal;

a ninth transistor, wherein a first electrode of the ninth transistor is connected to the first power supply, a second electrode of the ninth transistor is connected to a signal output terminal, and a gate electrode of the ninth transistor is connected to the first node;

a tenth transistor, wherein a first electrode of the tenth transistor is connected to the signal output terminal, a second electrode of the tenth transistor is connected to the second timing control terminal, and a gate electrode of the tenth transistor is connected to the second node;

a first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node; and

a second capacitor, wherein a first electrode of the second capacitor is connected to the second node, and a second electrode of the second capacitor is connected to the signal output terminal.

2 . The scan driving circuit according to claim 1 , wherein the first electrode of the seventh transistor is connected to the first node.

3 . The scan driving circuit according to claim 1 , wherein the shift register unit further comprises:

an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the first node, a second electrode of the eleventh transistor is connected to the first electrode of the seventh transistor, and a gate electrode of the eleventh transistor is connected to the first node.

4 . The scan driving circuit according to claim 3 , wherein the first transistor to the eleventh transistor are all P-type MOS transistors.

5 . The scan driving circuit according to claim 1 , further comprising a timing controller, wherein the timing controller comprises a first timing control signal line, a second timing control signal line and a third timing control signal line.

6 . The scan driving circuit according to claim 5 , wherein the first timing control signal line is configured to output a first timing control signal; the second timing control signal line is configured to output a second timing control signal; and the third timing control signal line is configured to output a third timing control signal.

7 . The scan driving circuit according to claim 6 , wherein the first timing control signal, the second timing control signal and the third timing control signal are square wave signals with same output frequency and a continuous low potential occupying ⅓ of a period.

8 . The scan driving circuit according to claim 6 , wherein the shift register unit is configured to perform a delay processing on a signal received from the signal input terminal under control of the first timing control signal, the second timing control signal and the third timing control signal, and a processed signal is output by the signal output terminal.

9 . The scan driving circuit according to claim 6 , wherein in a (3N-2)-th stage shift register unit, the first timing control terminal is connected to the first timing control signal line, the second timing control terminal is connected to the second timing control signal line, and the third timing control terminal is connected to the third timing control signal line, wherein N is a positive integer.

10 . The scan driving circuit according to claim 9 , wherein in a (3N-1)-th stage shift register unit, the first timing control terminal is connected to the third timing control signal line, the second timing control terminal is connected to the first timing control signal line, and the third timing control terminal is connected to the second timing control signal line, wherein N is a positive integer.

11 . The scan driving circuit according to claim 10 , wherein in a 3N-th stage shift register unit, the first timing control terminal is connected to the second timing control signal line, the second timing control terminal is connected to the third timing control signal line, and the third timing control terminal is connected to the first timing control signal line, wherein N is a positive integer.

12 . The scan driving circuit according to claim 5 , wherein the shift register unit at a previous stage outputs a scan signal to the shift register unit at a next stage, and the shift register unit at a last stage outputs a scan signal.

13 . A display panel, comprising a scan driving circuit, wherein the scan driving circuit comprises multiple stages of shift register units, and each of the shift register units comprises:

a first capacitor, wherein a first electrode of the first capacitor is connected to the first power supply, and a second electrode of the first capacitor is connected to the first node; and

a second capacitor, wherein a first electrode of the second capacitor is connected to the second node, and a second electrode of the second capacitor is connected to the signal output terminal.

14 . The display panel according to claim 13 , wherein the first electrode of the seventh transistor is connected to the first node.

15 . The display panel according to claim 13 , wherein the shift register unit further comprises:

16 . The display panel according to claim 13 , further comprising a timing controller, wherein the timing controller comprises a first timing control signal line, a second timing control signal line and a third timing control signal line.

17 . The display panel according to claim 16 , wherein the first timing control signal line is configured to output a first timing control signal; the second timing control signal line is configured to output a second timing control signal; and the third timing control signal line is configured to output a third timing control signal.

18 . The display panel according to claim 17 , wherein the first timing control signal, the second timing control signal and the third timing control signal are square wave signals with same output frequency and a continuous low potential occupying ⅓ of a period.

19 . The display panel according to claim 17 , wherein the shift register unit is configured to perform a delay processing on a signal received from the signal input terminal under control of the first timing control signal, the second timing control signal and the third timing control signal, and a processed signal is output by the signal output terminal.

20 . The display panel according to claim 16 , wherein the shift register unit at a previous stage outputs a scan signal to the shift register unit at a next stage, and the shift register unit at a last stage outputs a scan signal.