Semiconductor device
View Patent ↗A semiconductor device ( 300 A) includes a first layer ( 20 ) and a second layer ( 30 ) over the first layer. The first layer includes a logic circuit portion ( 23 ). The second layer includes a level shifter portion ( 24 ) and a pixel circuit ( 51 ). The logic circuit portion has a function of supplying a first signal for operating the level shifter portion to the level shifter portion. The level shifter portion has a function of supplying a second signal with a larger amplitude than the first signal to the pixel circuit. The logic circuit portion includes a transistor including silicon in a semiconductor layer where a channel is formed. Each of the level shifter portion and the pixel circuit includes a transistor including a metal oxide in a semiconductor layer where a channel is formed.
1 . A semiconductor device comprising:
a first layer; and
a second layer over the first layer,
wherein the first layer comprises a logic circuit portion,
wherein the second layer comprises a level shifter portion and a pixel circuit,
wherein the level shifter portion comprises a first transistor, a second transistor, and a third transistor,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein a gate of the second transistor is electrically connected to a first output terminal of the logic circuit portion,
wherein the logic circuit portion is configured to output a first signal for operating the level shifter portion to an input terminal portion of the level shifter portion,
wherein the level shifter portion is configured to supply a second signal with a larger amplitude than the first signal to the pixel circuit,
wherein the logic circuit portion comprises a transistor comprising silicon in a semiconductor layer where a channel is formed, and
wherein each of the level shifter portion and the pixel circuit comprises a transistor comprising a metal oxide in a semiconductor layer where a channel is formed.
2 . The semiconductor device according to claim 1 ,
the level shifter portion further comprising:
a fourth transistor;
a fifth transistor; and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein one terminal of the capacitor is electrically connected to the gate of the third transistor,
wherein a gate of the fifth transistor is electrically connected to a second output terminal of the logic circuit portion, and
wherein the other terminal of the capacitor is electrically connected to a third output terminal of the logic circuit portion.
3 . The semiconductor device according to claim 1 , wherein the metal oxide comprises at least one of indium and zinc.
4 . The semiconductor device according to claim 2 , wherein the metal oxide comprises at least one of indium and zinc.
5 . A semiconductor device comprising:
a first layer;
a second layer over the first layer; and
a third layer over the second layer,
wherein the first layer comprises a logic circuit portion,
wherein the second layer comprises a level shifter portion,
wherein the third layer comprises a pixel circuit,
wherein the level shifter portion comprises a first transistor, a second transistor, and a third transistor,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein a gate of the second transistor is electrically connected to a first output terminal of the logic circuit portion,
wherein the logic circuit portion is configured to output a first signal for operating the level shifter portion to an input terminal portion of the level shifter portion,
wherein the level shifter portion is configured to supply a second signal with a larger amplitude than the first signal to the pixel circuit,
wherein the logic circuit portion comprises a transistor comprising silicon in a semiconductor layer where a channel is formed, and
wherein each of the level shifter portion and the pixel circuit comprises a transistor comprising a metal oxide in a semiconductor layer where a channel is formed.
6 . The semiconductor device according to claim 5 , wherein the metal oxide comprises at least one of indium and zinc.
7 . The semiconductor device according to claim 5 ,
the level shifter portion further comprising:
a fourth transistor;
a fifth transistor; and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fifth transistor,
wherein one terminal of the capacitor is electrically connected to the gate of the third transistor,
wherein a gate of the fifth transistor is electrically connected to a second output terminal of the logic circuit portion, and
wherein the other terminal of the capacitor is electrically connected to a third output terminal of the logic circuit portion.
8 . The semiconductor device according to claim 7 , wherein the metal oxide comprises at least one of indium and zinc.