Display device with selective high-rate driving mode based on multi-channel data change detection
The present disclosure relates to a display driver integrated circuit and a display device. An example of the display driver integrated circuit includes a source driver and a timing controller. The source driver is configured to output a data voltage based on an image data to a first source line and a second source line. The timing controller is configured to receive first data and second data sequentially input to a first source channel that corresponds to the first source line, receive third data and fourth data sequentially input to a second source channel that corresponds to the second source line, perform an operation on the first data and the second data to generate a first change value, perform an operation on the third data and the fourth data to generate a second change value, and based on the first change value and the second change value, determine whether to toggle an output enable signal on an output of the second data in the first source line and an output of the fourth data in the second source line.
1 . A display device comprising:
a source driver configured to output a data voltage based on an image data to a first source line and a second source line, the second source line being different from the first source line; and
a timing controller configured to
receive first data and second data sequentially input to a first source channel that corresponds to the first source line,
receive third data and fourth data sequentially input to a second source channel that corresponds to the second source line, wherein the first source channel is different from the second source channel,
perform an operation on the first data and the second data to generate a first change value,
perform an operation on the third data and the fourth data to generate a second change value, and
based on the first change value and the second change value, determine whether to toggle an output enable signal on an output of the second data in the first source line and an output of the fourth data in the second source line.
2 . The display device of claim 1 , wherein the timing controller includes:
a first buffer configured to receive the first data,
a first subtractor configured to
receive the first data from the first buffer, and
perform a subtracting operation on the first data and the second data to generate the first change value,
a second buffer configured to receive the third data, and
a second subtractor configured to
receive the third data from the second buffer, and
perform a subtracting operation on the third data and the fourth data to generate the second change value.
3 . The display device of claim 2 , wherein the timing controller includes:
a first mode register configured to
receive the first change value, and
compare the first change value and a predetermined first reference value to output a first channel determination value on a data variation width of the first source channel, and
a second mode register configured to
receive the second change value, and
compare the second change value and the first reference value to output a second channel determination value on a data variation width of the second source channel.
4 . The display device of claim 3 , wherein the first reference value is stored in a one time programmable (OTP) data form.
5 . The display device of claim 1 , wherein
the timing controller includes a driving mode register configured to
receive a first channel determination value on the first source channel generated based on the first change value,
receive a second channel determination value on the second source channel generated based on the second change value, and
output an output enable control signal that determines whether to toggle the output enable signal.
6 . The display device of claim 5 , wherein
based on the output enable control signal being a low level signal, the output enable signal is toggled, and
based on the output enable control signal being a high level signal, the output enable signal is output with a predetermined level during a line time based on a horizontal synchronization signal.
7 . The display device of claim 6 , wherein the timing controller includes:
an OR operator configured to perform an OR operation on an output enable toggle signal and the output enable control signal, the output enable toggle signal being toggled for a predetermined period.
8 . The display device of claim 5 , wherein the timing controller includes:
a multiplexer configured to
receive an output enable toggle signal and a high level signal, the output enable toggle signal being toggled for a predetermined period, and
based on the output enable control signal, output the output enable toggle signal or the high level signal.
9 . The display device of claim 1 , wherein
the source driver is configured to
receive the output enable signal, and
intercept an output of the data voltage on the first source line and the second source line while the output enable signal is toggled.
10 . The display device of claim 9 , wherein
the source driver includes
a first output switch configured to control the output of the data voltage to the first source line in the first source channel, and
a second output switch configured to control the output of the data voltage to the second source line in the second source channel, and
the first output switch and the second output switch are operable by the output enable signal.
11 . The display device of claim 10 , wherein the source driver includes:
a first output enable buffer configured to provide the output enable signal to the first output switch, and
a second output enable buffer configured to provide the output enable signal to the second output switch.
12 . The display device of claim 11 , wherein
based on the output enable signal being output with a predetermined level for a line time based on a horizontal synchronization signal, the source driver is configured to perform a low power operation for the line time.
13 . The display device of claim 12 , wherein
for the line time, a dynamic current does not flow to the first output enable buffer and the second output enable buffer.
14 . A display device comprising:
a display panel configured to display an image through a first source line and a second source line based on a horizontal synchronization signal;
a source driver configured to output a data voltage to the first source line and the second source line based on an output enable signal; and
a timing controller configured to
determine, based on a first change value derived from data corresponding to a first source channel associated with the first source line and a second change value derived from data corresponding to a second source channel associated with the second source line, whether to operate in a first mode or a second mode, wherein the first source channel is different from the second source channel, and
toggle, in the first mode, the output enable signal at a first line time based on the horizontal synchronization signal, and output, in the second mode, the output enable signal with a predetermined level at a second line time, the second line time being sequential to the first line time.
15 . The display device of claim 14 , wherein
the source driver is configured to output the data voltage to the first source line and the second source line for the second line time based on the output enable signal.
16 . The display device of claim 15 , wherein
the source driver is configured not to perform an interception operation on an output of the data voltage for the second line time.
17 . The display device of claim 14 , wherein
the source driver includes a shift register, the shift register configured to
receive a latch signal from the timing controller, and
latch data that correspond to the data voltage based on the latch signal, and
the latch signal is toggled and is input to the shift register based on an edge of the output enable signal in the first line time.
18 . The display device of claim 17 , wherein
the data are latched to an output terminal of the shift register based on the toggling of the latch signal.
19 . The display device of claim 18 , wherein
at the first line time after the toggling of the latch signal, an output of the data voltage is intercepted by the output enable signal.
20 . A display device comprising:
a display panel including a plurality of pixels;
a gate driver connected to the plurality of pixels through a first gate line and a second gate line that are sequentially arranged, and the gate driver configured to activate the first gate line and the second gate line sequentially;
a source driver connected to the plurality of pixels through a plurality of source lines including a first source line and a second source line, the source driver configured to
output a data voltage to the plurality of pixels through the plurality of source lines based on an output enable signal,
be operable in a high-rate driving mode at a first line time that corresponds to activation of the first gate line corresponding to the output enable signal, and
turn off the high-rate driving mode at a second line time that corresponds to activation of the second gate line; and
a timing controller configured to
determine, based on a first change value derived from data corresponding to a first source channel associated with the first source line and a second change value derived from data corresponding to a second source channel associated with the second source line, whether to operate in the high-rate driving mode or an off mode, wherein the first source channel is different from the second source channel, and
provide the output enable signal to the source driver, the output enable signal being toggled at the first line time based on the source driver operating in the high-rate driving mode and being output with a predetermined level for the second line time based on the source driver operating in the off mode.