IP Library › Granted Patent US 12682827
Granted Patent B2
US 12682827 · App. 18/695,007 · Granted Jul 14, 2026

Scan control line driver module and display panel

Inventors: Ying-Hsiang Tseng (Shanghai, CN); Lina Xiao (Shanghai, CN); Qi Wang (Shanghai, CN); Jie Liu (Shanghai, CN)
Assignee: Everdisplay Optronics (Shanghai) Co., Ltd.
G09G3/22G09G2310/0286G09G2310/08G09G2330/021
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Quick Facts
Patent No.
US 12682827
App. No.
18/695,007
Granted
Jul 14, 2026
Kind
B2
Abstract

The present disclosure relates to the field of display panels, and provides a scan control line driver module and a display panel. The scan control line driver module comprises a multi-stage scan control line driver unit; the scan control line driver unit comprises a signal input terminal, a first timing control terminal, a second timing control terminal, a scan control line driver unit circuit and a signal output terminal; the scan control line driver unit circuit includes a control module, a reset module and an output setting module.

Claims (68)

1 . A scan control line driver module, comprising a multi-stage scan control line driver unit;

the scan control line driver unit comprises a signal input terminal, a first timing control terminal, a second timing control terminal, a scan control line driver unit circuit and a signal output terminal;

the scan control line driver unit circuit comprises a control module, a reset module and an output setting module;

the control module comprises:

a first transistor, wherein a gate of the first transistor is connected to the signal input terminal;

a second transistor, wherein a source of the second transistor is connected to the reset module, and a gate of the second transistor is connected to a drain of the first transistor;

a third transistor, wherein a source of the third transistor is connected to the drain of the first transistor, a gate of the third transistor is connected to the first timing control terminal, and a drain of the third transistor is connected to a second power supply;

a fourth transistor, wherein a source of the fourth transistor is connected to a drain of the second transistor, a gate of the fourth transistor is connected to the second timing control terminal, and a drain of the fourth transistor is connected to the second power supply; and

a third capacitor, wherein a first electrode of the third capacitor is connected to the drain of the second transistor, and a second electrode of the third capacitor is connected to the drain of the first transistor;

the reset module comprises:

a first node, wherein the source of the second transistor is connected to the first node;

a fifth transistor, wherein a gate of the fifth transistor is connected to the first node, and a drain of the fifth transistor is connected to the output setting module;

a sixth transistor, wherein a first terminal of the sixth transistor is connected to the second timing control terminal, a second terminal of the sixth transistor is connected to the output setting module, and a third terminal of the sixth transistor is connected to the first node;

a seventh transistor, wherein a source of the seventh transistor is connected to a first power supply, a gate of the seventh transistor is connected to the first node, and a drain of the seventh transistor is connected to the signal output terminal;

a twelfth transistor, wherein a source of the twelfth transistor is connected to the first power supply, a gate of the twelfth transistor is connected to the first timing control terminal, and a drain of the twelfth transistor is connected to a source of the fifth transistor; and

a second capacitor, wherein a first electrode of the second capacitor is connected to the first power supply, and a second electrode of the second capacitor is connected to the first node.

2 . The scan control line driver module according to claim 1 , wherein a source of the first transistor is connected to the first timing control terminal.

3 . The scan control line driver module according to claim 1 , wherein a source of the first transistor is connected to the first power supply.

4 . The scan control line driver module according to claim 2 , wherein the output setting module comprises:

a second node, wherein the drain of the fifth transistor is connected to the second node, and the second terminal of the sixth transistor is connected to the second node;

an eighth transistor, wherein a source of the eighth transistor is connected to the signal output terminal, and a drain of the eighth transistor is connected to the first timing control terminal;

a ninth transistor, wherein a gate of the ninth transistor is connected to the second power supply, and a drain of the ninth transistor is connected to a gate of the eighth transistor;

a tenth transistor, wherein a source of the tenth transistor is connected to the second node, a gate of the tenth transistor is connected to the second power supply, and a drain of the tenth transistor is connected to a source of the ninth transistor;

an eleventh transistor, wherein a first terminal of the eleventh transistor is connected to the second node, a second terminal of the eleventh transistor is connected to the second timing control terminal, and a third terminal of the eleventh transistor is connected to the signal input terminal; and

a first capacitor, wherein a first electrode of the first capacitor is connected to the signal output terminal, and a second electrode of the first capacitor is connected to the gate of the eighth transistor.

5 . The scan control line driver module according to claim 1 , further comprising: a timing controller, configured to output a first timing control signal and a second timing control signal.

6 . The scan control line driver module according to claim 5 , wherein the scan control line driver unit circuit is configured to perform delay processing on a signal received from the signal input terminal under control of the first timing control signal and the second timing control signal, and the processed signal is output by the signal output terminal.

7 . The scan control line driver module according to claim 5 , wherein a scanning signal is output by a previous-stage scan control line driver unit to a next-stage scan control line driver unit, and a scanning signal is output by a last-stage scan control line driver unit.

8 . The scan control line driver module according to claim 5 , wherein a first timing control terminal of an odd-stage scan control line driver unit is configured to receive the first timing control signal, and a second timing control terminal of the odd-stage scan control line driver unit is configured to receive the second timing control signal.

9 . The scan control line driver module according to claim 5 , wherein a first timing control terminal of an even-stage scan control line driver unit is configured to receive the second timing control signal, and a second timing control terminal of the even-stage scan control line driver unit is configured to receive the first timing control signal.

10 . The scan control line driver module according to claim 5 , wherein the timing controller comprises a first clock signal line configured to output the first timing control signal and a second clock signal line configured to output the second timing control signal, and the first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

11 . The scan control line driver module according to claim 4 , wherein the first to twelfth transistors are all P-type MOS transistors.

12 . A display panel, comprising a scan control line driver module, wherein the scan control line driver module comprises a multi-stage scan control line driver unit;

the scan control line driver unit comprises a signal input terminal a first timing control terminal, a second timing control terminal, a scan control line driver unit circuit and a signal output terminal;

the scan control line driver unit circuit comprises a control module a reset module and an output setting module;

the control module comprises:

a first transistor, wherein a gate of the first transistor is connected to the signal input terminal;

a second transistor, wherein a source of the second transistor is connected to the reset module, and a gate of the second transistor is connected to a drain of the first transistor;

a third transistor, wherein a source of the third transistor is connected to the drain of the first transistor, a gate of the third transistor is connected to the first timing control terminal, and a drain of the third transistor is connected to a second power supply;

a fourth transistor, wherein a source of the fourth transistor is connected to a drain of the second transistor, a gate of the fourth transistor is connected to the second timing control terminal, and a drain of the fourth transistor is connected to the second power supply; and

a third capacitor, wherein a first electrode of the third capacitor is connected to the drain of the second transistor, and a second electrode of the third capacitor is connected to the drain of the first transistor;

the reset module comprises:

a first node, wherein the source of the second transistor is connected to the first node;

a fifth transistor, wherein a gate of the fifth transistor is connected to the first node, and a drain of the fifth transistor is connected to the output setting module;

a sixth transistor, wherein a first terminal of the sixth transistor is connected to the second timing control terminal, a second terminal of the sixth transistor is connected to the output setting module, and a third terminal of the sixth transistor is connected to the first node;

a seventh transistor, wherein a source of the seventh transistor is connected to a first power supply, a gate of the seventh transistor is connected to the first node, and a drain of the seventh transistor is connected to the signal output terminal;

a twelfth transistor, wherein a source of the twelfth transistor is connected to the first power supply, a gate of the twelfth transistor is connected to the first timing control terminal, and a drain of the twelfth transistor is connected to a source of the fifth transistor; and

a second capacitor, wherein a first electrode of the second capacitor is connected to the first power supply, and a second electrode of the second capacitor is connected to the first node.

13 . The scan control line driver module according to claim 3 , wherein the output setting module comprises:

a second node, wherein the drain of the fifth transistor is connected to the second node, and the second terminal of the sixth transistor is connected to the second node;

an eighth transistor, wherein a source of the eighth transistor is connected to the signal output terminal, and a drain of the eighth transistor is connected to the first timing control terminal;

a ninth transistor, wherein a gate of the ninth transistor is connected to the second power supply, and a drain of the ninth transistor is connected to a gate of the eighth transistor;

a tenth transistor, wherein a source of the tenth transistor is connected to the second node, a gate of the tenth transistor is connected to the second power supply, and a drain of the tenth transistor is connected to a source of the ninth transistor;

an eleventh transistor, wherein a first terminal of the eleventh transistor is connected to the second node, a second terminal of the eleventh transistor is connected to the second timing control terminal, and a third terminal of the eleventh transistor is connected to the signal input terminal; and

a first capacitor, wherein a first electrode of the first capacitor is connected to the signal output terminal, and a second electrode of the first capacitor is connected to the gate of the eighth transistor.

14 . The display panel according to claim 12 , wherein a source of the first transistor is connected to the first timing control terminal.

15 . The display panel according to claim 12 , wherein a source of the first transistor is connected to the first power supply.

16 . The display panel according to claim 14 , wherein the output setting module comprises:

a second node, wherein the drain of the fifth transistor is connected to the second node, and the second terminal of the sixth transistor is connected to the second node;

an eighth transistor, wherein a source of the eighth transistor is connected to the signal output terminal, and a drain of the eighth transistor is connected to the first timing control terminal;

a ninth transistor, wherein a gate of the ninth transistor is connected to the second power supply, and a drain of the ninth transistor is connected to a gate of the eighth transistor;

a tenth transistor, wherein a source of the tenth transistor is connected to the second node, a gate of the tenth transistor is connected to the second power supply, and a drain of the tenth transistor is connected to a source of the ninth transistor;

an eleventh transistor, wherein a first terminal of the eleventh transistor is connected to the second node, a second terminal of the eleventh transistor is connected to the second timing control terminal, and a third terminal of the eleventh transistor is connected to the signal input terminal; and

a first capacitor, wherein a first electrode of the first capacitor is connected to the signal output terminal, and a second electrode of the first capacitor is connected to the gate of the eighth transistor.

17 . The display panel according to claim 12 , wherein the scan control line driver module further comprises: a timing controller, configured to output a first timing control signal and a second timing control signal.

18 . The display panel according to claim 17 , wherein the scan control line driver unit circuit is configured to perform delay processing on a signal received from the signal input terminal under control of the first timing control signal and the second timing control signal, and the processed signal is output by the signal output terminal.

19 . The display panel according to claim 17 , wherein a scanning signal is output by a previous-stage scan control line driver unit to a next-stage scan control line driver unit, and a scanning signal is output by a last-stage scan control line driver unit.

20 . The display panel according to claim 17 , wherein a first timing control terminal of an odd-stage scan control line driver unit is configured to receive the first timing control signal, and a second timing control terminal of the odd-stage scan control line driver unit is configured to receive the second timing control signal.