Pixel of a display device, and display device
A pixel includes: a first transistor including a gate coupled to a first node, a first terminal, and a second terminal coupled to a second node; a first capacitor coupled between the first and second nodes; a second transistor including a gate receiving a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first node; a third transistor including a gate receiving a second signal, a first terminal receiving a reference voltage, and a second terminal coupled to the first node; a fourth transistor including a gate receiving a third signal, a first terminal coupled to the second node, and a second terminal receiving an initialization voltage; a light emitting element including an anode; and a fifth transistor including a gate receiving a fourth signal, a first terminal coupled to the second node, and a second terminal coupled to the anode.
1 . An electronic device comprising:
a processor configured to provide input image data; and
a display device configured to receive the input image data from the processor, and to display an image based on the input image data, the display device including a pixel, the pixel comprising:
a first transistor including a gate coupled to a first node, a drain coupled to a first power supply voltage line, and a source coupled to a second node;
a first capacitor coupled between the first node and the second node;
a second transistor including a gate, which receives a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first node;
a third transistor including a gate, which receives a second signal, a first terminal, which receives a reference voltage, and a second terminal coupled to the first node;
a fourth transistor including a gate, which receives a third signal, a first terminal coupled to the second node, and a second terminal, which receives an initialization voltage;
a light emitting element including an anode, and a cathode coupled to a second power supply voltage line; and
a fifth transistor including a gate, which receives a fourth signal, a drain coupled to the second node, and a source coupled to the anode,
wherein the first and fifth transistors are n-type metal oxide semiconductor (NMOS) transistors,
wherein, in a threshold voltage compensation period, a power supply voltage is applied to the drain of the first transistor through the first power supply voltage line, the reference voltage is applied to the gate of the first transistor through the third transistor, the third transistor transfers the reference voltage to the first node, and the first transistor changes a voltage of the second node to a voltage corresponding to a threshold voltage of the first transistor subtracted from the reference voltage,
wherein during the threshold voltage compensation period, the third transistor is turned on, and the second, fourth, and fifth transistors are turned off.
2 . The electronic device of claim 1 , wherein, during the threshold voltage compensation period, the fifth transistor is turned off to separate the second node from the anode.
3 . The electronic device of claim 1 , wherein at least one of the first through fifth transistors is implemented with an oxide transistor.
4 . The electronic device of claim 1 , further comprising:
a sixth transistor including a gate, which receives the third signal, a first terminal coupled to the anode, and a second terminal, which receives the initialization voltage.
5 . The electronic device of claim 1 , further comprising:
a sixth transistor including a gate, which receives the third signal, a first terminal coupled to the source of the first transistor, and a second terminal, which receives the initialization voltage.
6 . The electronic device of claim 1 , further comprising:
a sixth transistor including a gate, which receives the second signal, a first terminal coupled to the anode, and a second terminal, which receives the initialization voltage.
7 . The electronic device of claim 1 , further comprising:
a sixth transistor including a gate, which receives the second signal, a first terminal coupled to the source of the first transistor, and a second terminal, which receives the initialization voltage.
8 . The electronic device of claim 1 , further comprising:
a seventh transistor including a gate, which receives a fifth signal, a first terminal coupled to the first power supply voltage line, and a second terminal coupled to the drain of the first transistor.
9 . The electronic device of claim 1 , further comprising:
a second capacitor coupled between the first power supply voltage line and the second node.
10 . The electronic device of claim 1 , wherein, when a current characteristic of the first transistor is changed, a voltage of the second node is changed by a current of the first transistor to compensate for a change of the current characteristic of the first transistor.
11 . The electronic device of claim 1 , wherein the data line and an electrode of the source of the first transistor do not overlap each other such that a second parasitic capacitor between the second node and the data line has a capacitance less than a capacitance of a first parasitic capacitor between the anode and the data line.
12 . The electronic device of claim 1 , wherein each frame period for the pixel includes:
an initialization period in which the first node and the second node are initialized;
the threshold voltage compensation period in which a threshold voltage of the first transistor is stored in the first capacitor;
a data writing period in which a data voltage provided through the data line is transferred to the first node;
a current characteristic compensation period in which a change of a current characteristic of the first transistor is compensated; and
an emission period in which the light emitting element emits light.
13 . The electronic device of claim 12 , wherein, in the current characteristic compensation period, the second signal, the third signal and the fourth signal have an inactive level, the drain of the first transistor receives the power supply voltage provided from the first power supply voltage line, the first transistor is turned on to apply a current to the second node, and the fifth transistor is turned off in response to the fourth signal having the inactive level to separate the second node from the anode.
14 . The electronic device of claim 12 , wherein the data writing period overlaps the current characteristic compensation period.
15 . The electronic device of claim 12 , wherein the data writing period is separate from the current characteristic compensation period.
16 . An electronic device comprising:
a processor configured to provide input image data; and
a display device configured to receive the input image data from the processor, and to display an image based on the input image data, the display device including a pixel, the pixel comprising:
a first transistor including a gate coupled to a first node, a drain coupled to a first power supply voltage line, and a source coupled to a second node;
a first capacitor coupled between the first node and the second node;
a second transistor including a gate, which receives a first signal, a first terminal coupled to a data line, and a second terminal coupled to the first node;
a third transistor including a gate, which receives a second signal, a first terminal, which receives a reference voltage, and a second terminal coupled to the first node;
a fourth transistor including a gate, which receives a third signal, a first terminal coupled to the second node, and a second terminal, which receives an initialization voltage;
a light emitting element including an anode, and a cathode coupled to a second power supply voltage line;
a fifth transistor including a gate, which receives a fourth signal, a drain coupled to the second node, and a source coupled to the anode; and
a sixth transistor including a gate, which receives the second signal, a first terminal coupled to the anode, and a second terminal, which receives the initialization voltage,
wherein the third and sixth transistors are n-type metal oxide semiconductor (NMOS) transistors,
wherein, in a threshold voltage compensation period, a power supply voltage is applied to the drain of the first transistor through the first power supply voltage line, and the reference voltage is applied to the gate of the first transistor through the third transistor,
wherein the threshold voltage compensation period starts when the fourth transistor is turned off and ends when the second transistor is turned on and the third transistor is turned off, and the fifth transistor is turned off during the threshold voltage compensation period.
17 . The electronic device of claim 16 , further comprising:
a seventh transistor including a gate, which receives a fifth signal, a first terminal coupled to the first power supply voltage line, and a second terminal coupled to the drain of the first transistor.