Gate driving circuit and display apparatus including the same

1 . A micro-LED display apparatus, comprising:

a timing controller configured to output image data;

a display panel including a plurality of pixel arrays that are connected to a data line; and

a data driver configured to generate a data voltage based on the image data and apply the data voltage to the data line,

wherein a pixel array of the plurality of pixel arrays comprises a gate in array (GIA) circuit that provides a scan signal to a subpixel of the pixel array, and

wherein the GIA circuit comprises:

a first transistor including a gate electrode connected to a QB node of the GIA circuit, a source electrode that receives a gate high voltage, and a drain electrode that outputs an N-th carry signal;

a second transistor including a gate electrode connected to a Q node of the GIA circuit, a source electrode that outputs the N-th carry signal, and a drain electrode that receives an N-th carry clock signal;

a third transistor including a gate electrode connected to the same QB node as the gate electrode of the first transistor, a source electrode that receives the gate high voltage, and a drain electrode that outputs an N-th scan signal;

a fourth transistor including a gate electrode connected to the same Q node as the gate electrode of the second transistor, a source electrode that outputs the N-th scan signal, and a drain electrode that receives an N-th clock signal;

a first gate driver configured to provide a first scan signal to the subpixel; and

a second gate driver configured to provide a second scan signal to the subpixel,

wherein a pulse width of the second scan signal is shorter than a pulse width of the first scan signal, and

wherein a pulse width of a data voltage signal representing the data voltage is longer than the pulse width of the first scan signal.

2 . The micro-LED display apparatus of claim 1 , wherein the display panel includes a first GIA region, a second GIA region, and a third GIA region.

3 . The micro-LED display apparatus of claim 1 , wherein the first gate driver and the second gate driver further comprise a capacitor that receives the N-th scan signal and is connected to the Q node.

4 . The micro-LED display apparatus of claim 1 , wherein the N-th carry signal is a same as the N-th scan signal, and

wherein the N-th carry clock signal is a same as the N-th clock signal.

5 . A gate driving circuit, comprising:

a gate in array (GIA) circuit configured to provide a scan signal to a subpixel, the GIA circuit comprising:

a first transistor including a gate electrode connected to a QB node of the GIA circuit, a source electrode that receives a gate high voltage, and a drain electrode that outputs an N-th carry signal;

a second transistor including a gate electrode connected to a Q node of the GIA circuit, a source electrode that outputs the N-th carry signal, and a drain electrode that receives an N-th carry clock signal;

a third transistor including a gate electrode connected to the same QB node as the gate electrode of the first transistor, a source electrode that receives the gate high voltage, and a drain electrode that outputs an N-th scan signal;

a fourth transistor including a gate electrode connected to the same Q node as the gate electrode of the second transistor, a source electrode that outputs the N-th scan signal, and a drain electrode that receives an N-th clock signal;

a first gate driver configured to provide a first scan signal to the subpixel; and

a second gate driver configured to provide a second scan signal to the subpixel,

wherein a pulse width of the second scan signal is shorter than a pulse width of the first scan signal, and

wherein a pulse width of a data voltage is longer than the pulse width of the first scan signal.

6 . The gate driving circuit of claim 5 , wherein the GIA circuit is on a first GIA region, a second GIA region, and a third GIA region of a display panel.

7 . The gate driving circuit of claim 5 , wherein the first gate driver and the second gate driver further comprise a capacitor that receives the N-th scan signal and is connected to the Q node.

8 . The gate driving circuit of claim 5 , wherein the N-th carry signal is a same as the N-th scan signal, and

wherein the N-th carry clock signal is the same as the N-th clock signal.