IP Library Granted Patent US 12682840
Granted Patent B2
US 12682840 · App. 19/185,207 · Granted Jul 14, 2026

Display device

Inventors: Junhyun Park (Yongin-si, KR); Hyeongseok Kim (Yongin-si, KR); Heejean Park (Yongin-si, KR); Sunhwa Lee (Yongin-si, KR); Mukyung Jeon (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
G09G3/32G09G2300/0842G09G2310/0267G09G2330/06
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12682840
App. No.
19/185,207
Granted
Jul 14, 2026
Kind
B2
Abstract

A display device includes: an active layer on a substrate; a first switching transistor including a part of the active layer; a second switching transistor including a part of the active layer and in a same plane as at least a part of the first switching transistor in a first direction in a plan view; a first capacitor on the active layer and connected to the second switching transistor; a second capacitor on the active layer and connected to the first switching transistor; a first gate line extending in the first direction and connected to a gate electrode of each of the first and second switching transistors; and a light emitting element on the first gate line.

Claims (70)

1 . A display device comprising:

an active layer on a substrate;

a first switching transistor including a part of the active layer;

a second switching transistor including a part of the active layer and positioned in a first direction from the first switching transistor;

a first capacitor on the active layer and connected to the first switching transistor and the second switching transistor;

a second capacitor on the active layer, connected to the first switching transistor, and at least partially overlapping the first capacitor in a plan view; and

a first gate line extending in the first direction and connected to a gate electrode of each of the first and second switching transistors.

2 . The display device of claim 1 , wherein the active layer includes:

an active pattern partially overlapping the first and second capacitors;

a first extension part connected to the active pattern; and

a second extension part connected to the active pattern and spaced apart from the first extension part in the first direction, and

wherein the first switching transistor includes a part of the first extension part and the second switching transistor includes a part of the second extension part.

3 . The display device of claim 2 , further comprising:

a second gate line adjacent to the first gate line and extending in the first direction; and

a third gate line adjacent to the second gate line and extending in the first direction,

wherein the second and third gate lines partially overlap the first and second extension parts, respectively.

4 . The display device of claim 3 , further comprising:

a third switching transistor including a part of the first extension part; and

a fourth switching transistor including a part of the second extension part,

wherein the second gate line is connected to a gate electrode of the third switching transistor and the third gate line is connected to a gate electrode of the fourth switching transistor, and

wherein the second gate line is configured to receive a data write signal and the third gate line is configured to receive a data initialization gate signal.

5 . The display device of claim 2 , wherein the first gate line partially overlaps each of the first and second extension parts.

6 . The display device of claim 1 , wherein the active layer continuously extends on the substrate.

7 . The display device of claim 1 , wherein the first gate line is configured to receive a compensation gate signal.

8 . The display device of claim 1 , wherein the first capacitor is a storage capacitor and the second capacitor is a hold capacitor.

9 . The display device of claim 1 , wherein the first gate line is adjacent to the first and second capacitors.

10 . The display device of claim 1 , further comprising:

a transfer line in a peripheral area surrounding at least a part of a display area of the substrate, extending in a second direction crossing the first direction, and configured to receive a DC power supply voltage,

wherein the active layer is connected to the transfer line in the first direction.

11 . A display device comprising:

an active layer on a substrate;

a driving transistor including a part of the active layer and configured to generate a driving current;

a first switching transistor including a part of the active layer and connected to the driving transistor;

a second switching transistor including a part of the active layer;

a first capacitor on the active layer and connected to the second switching transistor;

a second capacitor on the first capacitor and at least partially overlapping the first capacitor in a plan view; and

a first gate line extending in a first direction and connected to a gate electrode of each of the first and second switching transistors.

12 . The display device of claim 11 , wherein the active layer includes:

an active pattern partially overlapping the first and second capacitors;

a first extension part connected to the active pattern; and

a second extension part connected to the active pattern and spaced apart from the first extension part in the first direction, and

wherein the first switching transistor includes a part of the first extension part and the second switching transistor includes a part of the second extension part.

13 . The display device of claim 12 , further comprising:

a second gate line adjacent to the first gate line and extending in the first direction; and

a third gate line adjacent to the second gate line and extending in the first direction,

wherein the second and third gate lines partially overlap the first and second extension parts, respectively.

14 . The display device of claim 13 , further comprising:

a fourth switching transistor including a part of the first extension part; and

a fifth switching transistor including a part of the second extension part,

wherein the second gate line is connected to a gate electrode of the fourth switching transistor and the third gate line is connected to a gate electrode of the fifth switching transistor, and

wherein the second gate line is configured to receive a data write signal and the third gate line is configured to receive a data initialization gate signal.

15 . The display device of claim 12 , wherein the first gate line partially overlaps each of the first and second extension parts.

16 . The display device of claim 11 , further comprising:

a third switching transistor including a part of the active layer and connected to the first capacitor and the second capacitor,

wherein the first gate line is connected to a gate electrode of the third switching transistor.

17 . The display device of claim 11 , wherein the active layer continuously extends on the substrate.

18 . The display device of claim 11 , wherein the first gate line is configured to receive a compensation gate signal.

19 . The display device of claim 11 , wherein the first gate line is adjacent to the first and second capacitors.

20 . An electronic device comprising:

a display device;

a processor configured to control the display device; and

a power supply configured to supply power to the display device,

wherein the display device includes:

an active layer on a substrate;

a driving transistor including a part of the active layer and configured to generate a driving current;

a first switching transistor including a part of the active layer and connected to the driving transistor;

a second switching transistor including a part of the active layer;

a first capacitor on the active layer and connected to the second switching transistor;

a second capacitor on the first capacitor and at least partially overlapping the first capacitor in a plan view; and

a first gate line extending in a first direction and connected to a gate electrode of each of the first and second switching transistors.