Semiconductor apparatus, display device, and electronic device
One embodiment of the present invention relates to a common semiconductor apparatus for driving two different circuits. The semiconductor apparatus is capable of switching a plurality of signal potentials and sequentially outputting the plurality of signal potentials to the outside. The semiconductor apparatus can make one of two different circuits arranged in a matrix operate in all the rows and can make the other circuit operate in all the rows or only in a specific row. For example, in the case where the semiconductor apparatus is applied to a row driver that drives pixels of a display device in which sensor elements are incorporated, the operation of display elements in pixels in all the rows and the operation of sensor elements in pixels in all the rows or in the specific row can be switched.
1 . A semiconductor apparatus comprising:
a first block;
a second block;
a third block; and
a first switch circuit,
wherein the first block, the second block, and the third block each include a plurality of flip-flop circuits and a plurality of output circuits,
wherein a first pair of output circuits of the plurality of output circuits is electrically connected to a first flip-flop circuit of the plurality of flip-flop circuits,
wherein a second pair of output circuits of the plurality of output circuits is electrically connected to a second flip-flop circuit of the plurality of flip-flop circuits,
wherein in each of the first block, the second block, and the third block, the plurality of flip-flop circuits are provided so as to form a cascade,
wherein a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the first block, a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the second block, a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the second block, and a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the third block are electrically connected to the first switch circuit,
wherein one output circuit of the first pair of output circuits includes a second switch circuit, a first circuit, and a second circuit,
wherein the first flip-flop circuit is electrically connected to a first switch of the second switch circuit and a second switch of the second switch circuit,
wherein the first switch is electrically connected to the first circuit and the second switch is electrically connected to the second circuit,
wherein a pulse width control signal is input to a third switch of the second switch circuit and a fourth switch of the second switch circuit, and
wherein the third switch is electrically connected to the first circuit and the fourth switch is electrically connected to the second circuit.
2 . The semiconductor apparatus according to claim 1 , wherein the first switch circuit is configured to select one of an operation of outputting a signal potential from the first block, the second block, and the third block and an operation of outputting a signal potential from the first block and the third block but not from the second block.
3 . The semiconductor apparatus according to claim 1 , wherein the second switch circuit is configured to select one of conduction between the first flip-flop circuit and the first circuit and conduction between the first flip-flop circuit and the second circuit.
4 . The semiconductor apparatus according to claim 1 ,
wherein the first flip-flop circuit outputs a first signal potential to the second switch circuit,
wherein the second switch circuit outputs a second signal potential based on the first signal potential to the first circuit,
wherein the second switch circuit outputs a third signal potential based on the first signal potential to the second circuit,
wherein the first circuit outputs a fourth signal potential based on the second signal potential, and
wherein the second circuit outputs a fifth signal potential based on the third signal potential.
5 . The semiconductor apparatus according to claim 4 ,
wherein a sixth signal potential or a seventh signal potential is input to the first switch circuit and the second switch circuit,
wherein when the sixth signal potential is input to the first switch circuit and the second switch circuit, the first circuit outputs an eighth signal potential, and
wherein when the seventh signal potential is input to the first switch circuit and the second switch circuit, the second circuit outputs a ninth signal potential.
6 . The semiconductor apparatus according to claim 1 , wherein when the last stage in the first block is a fourth stage, the last stage in the second block is a 4n-th stage (n is an integer greater than or equal to 2) and the last stage in the third block is a 4n+4-th stage.
7 . The semiconductor apparatus according to claim 1 ,
wherein the first flip-flop circuit is directly connected to the first switch of the second switch circuit and the second switch of the second switch circuit,
wherein the first switch is directly connected to the first circuit and the second switch is directly connected to the second circuit, and
wherein the third switch is directly connected to the first circuit and the fourth switch is directly connected to the second circuit.
8 . A display device comprising:
a first block;
a second block;
a third block;
a first switch circuit; and
a pixel,
wherein the first block, the second block, and the third block each include a plurality of flip-flop circuits and a plurality of output circuits,
wherein a first pair of output circuits of the plurality of output circuits is electrically connected to a first flip-flop circuit of the plurality of flip-flop circuits,
wherein a second pair of output circuits of the plurality of output circuits is electrically connected to a second flip-flop circuit of the plurality of flip-flop circuits,
wherein in each of the first block, the second block, and the third block, the plurality of flip-flop circuits are provided so as to form a cascade,
wherein a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the first block, a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the second block, a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the second block, and a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the third block are electrically connected to the first switch circuit,
wherein one output circuit of the first pair of output circuits includes a second switch circuit, a first circuit, and a second circuit,
wherein the first flip-flop circuit is electrically connected to a first switch of the second switch circuit and a second switch of the second switch circuit,
wherein the first switch is electrically connected to the first circuit and the second switch is electrically connected to the second circuit,
wherein a pulse width control signal is input to a third switch of the second switch circuit and a fourth switch of the second switch circuit,
wherein the third switch is electrically connected to the first circuit and the fourth switch is electrically connected to the second circuit,
wherein the pixel includes a third circuit including a display element and a fourth circuit including a light-receiving element, and
wherein the first circuit is electrically connected to the third circuit and the second circuit is electrically connected to the fourth circuit.
9 . The display device according to claim 8 ,
wherein the display element is a light-emitting element, and
wherein the light-receiving element shares an electrode with the light-emitting element.
10 . The display device according to claim 8 ,
wherein the third circuit and the fourth circuit each include a transistor containing a metal oxide in a channel formation region,
wherein the metal oxide includes In, Zn, and M, and
wherein M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.
11 . An electronic device comprising the display device according to claim 8 .
12 . A semiconductor apparatus comprising:
a first block;
a second block;
a third block; and
a first switch circuit,
wherein the first block, the second block, and the third block each include a plurality of flip-flop circuits and a plurality of output circuits,
wherein a first pair of output circuits of the plurality of output circuits is electrically connected to a first flip-flop circuit of the plurality of flip-flop circuits,
wherein a second pair of output circuits of the plurality of output circuits is electrically connected to a second flip-flop circuit of the plurality of flip-flop circuits,
wherein in each of the first block, the second block, and the third block, the plurality of flip-flop circuits are provided so as to form a cascade,
wherein a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the first block, a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the second block, a flip-flop circuit of the plurality of flip-flop circuits in the last stage of the second block, and a flip-flop circuit of the plurality of flip-flop circuits in a first stage of the third block are electrically connected to the first switch circuit,
wherein one output circuit of the first pair of output circuits includes a second switch circuit, a first circuit, and a second circuit,
wherein the first flip-flop circuit is electrically connected to a first switch of the second switch circuit and a second switch of the second switch circuit,
wherein the first switch is electrically connected to the first circuit and the second switch is electrically connected to the second circuit,
wherein a pulse width control signal is input to a third switch of the second switch circuit and a fourth switch of the second switch circuit,
wherein the third switch is electrically connected to the first circuit and the fourth switch is electrically connected to the second circuit,
wherein the third switch is a first transistor and the fourth switch is a second transistor,
wherein a gate of the first transistor is electrically connected to a first electrode of a first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a second electrode of the first capacitor and one of a source and a drain of a third transistor of the first circuit,
wherein a gate of the second transistor is electrically connected to a first electrode of a second capacitor, and
wherein one of a source and a drain of the second transistor is electrically connected to a second electrode of the second capacitor and one of a source and a drain of a fourth transistor of the second circuit.
13 . The semiconductor apparatus according to claim 12 ,
wherein a gate of the third transistor is electrically connected to one of a source and a drain of a fifth transistor of the first circuit,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the first switch,
wherein a gate of the fourth transistor is electrically connected to one of a source and a drain of a sixth transistor of the second circuit, and
wherein the other of the source and the drain of the sixth transistor is electrically connected to the second switch.