IP Library Granted Patent US 12682870
Granted Patent B2
US 12682870 · App. 19/187,684 · Granted Jul 14, 2026

Systems and methods for improving operating characteristics of displays

Inventors: Stephen John Hart (San Juan Capistrano, CA); Rock Edward Kent (Estacada, OR); Howard V. Goetz (Tigard, OR); James L. Sanford (Wappingers Falls, NY); Nicholas W. Melena (Phoenix, AZ)
Assignee: Snap Inc.
G09G5/395G09G3/36G09G2300/0478
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Quick Facts
Patent No.
US 12682870
App. No.
19/187,684
Granted
Jul 14, 2026
Kind
B2
Abstract

Systems and methods for improving operating characteristics of displays such as liquid crystal on silicon displays.

Claims (62)

1 . A display system, comprising:

a display comprising a plurality of pixels; and

a display driver to:

store a plurality of bit-plane sequences, each bit-plane sequence comprising baseline voltage values for a plurality of bit-planes;

measure a first phase ripple value of the display using the baseline voltage values;

generate a modified bit-plane sequence by adding a voltage offset to at least one baseline voltage value of at least one bit-plane of the plurality of bit-planes of a first bit-plane sequence of the plurality of bit-plane sequences;

measure a second phase ripple value of the display using the modified bit-plane sequence; and

select between the first bit-plane sequence and the modified bit-plane sequence based on comparing the first and second phase ripple values.

2 . The display system of claim 1 , wherein:

the display driver maintains DC-balance by applying equal and opposite voltage offsets to corresponding bit-planes in positive and negative polarity sub-frames.

3 . The display system of claim 1 , further comprising:

a mixed-signal chip coupled to the display driver to:

receive voltage control commands from the display driver; and

generate pixel electrode voltages for the display according to the voltage values of the selected first bit-plane sequence or modified bit-plane sequence.

4 . The display system of claim 1 , wherein:

the voltage offset is between 0.1V and 0.2V.

5 . The display system of claim 1 , wherein:

each bit-plane sequence includes one or more groups of 1-values spaced apart from one another within the bit-plane sequence by one or more groups of 0-values.

6 . The display system of claim 5 , wherein:

each of the one or more groups of 1-values has a respective number of bit-planes that is within one bit-plane of the respective number of bit-planes of each other group of 1-values.

7 . The display system of claim 6 , wherein:

each of the one or more groups of 0-values has a respective number of bit-planes that is within one bit-plane of the respective number of bit-planes of each other group of 0-values.

8 . The display system of claim 7 , wherein:

for each sequence of bit-planes where:

a length of the bit-plane sequence is a first length;

a number P represents the number of 1-values in the bit-plane sequence; and

the number P of 1-values is greater than one and less than the first length minus 2,

the number of 1-values being distributed across a length of the bit-plane sequence according to a spacing D that is determined as the first length divided by P.

9 . The display system of claim 1 , wherein:

the display driver is further configured to apply the selected bit-plane sequence or modified selected bit-plane sequence to a pixel of the plurality of pixels.

10 . The display system of claim 9 , wherein:

the display driver is further configured to select the bit-plane sequence from the plurality of bit-plane sequences based on a phase-shift value of the pixel.

11 . The display system of claim 10 , wherein:

the display driver stores the plurality of bit-plane sequences in a display table including a plurality of rows, each row of the display table including a corresponding bit-plane sequence of the plurality of bit-plane sequences, each row associated with one of a plurality of phase-shift values for each of the pixels in the display.

12 . The display system of claim 1 , wherein:

the display driver applies the bit-plane sequences to the display during a frame having an associated frame time; and

each bit-plane in a bit-plane sequence corresponds to a respective time period such that the bit-plane sequence repeats an integer number of times within the frame time.

13 . A display driver, comprising:

storage means to store a plurality of bit-plane sequences, each bit-plane sequence comprising baseline voltage values for a plurality of bit-planes;

first measurement means to measure a first phase ripple value of a display using the baseline voltage values;

bit-plane modification means to generate a modified bit-plane sequence by adding a voltage offset to at least one baseline voltage value of at least one bit-plane of the plurality of bit-planes of a first bit-plane sequence of the plurality of bit-plane sequences;

second measurement means to measure a second phase ripple value of the display using the modified bit-plane sequence; and

selection means to select between the first bit-plane sequence and the modified bit-plane sequence based on comparing the first and second phase ripple values.

14 . A method, comprising:

storing a plurality of bit-plane sequences, each bit-plane sequence comprising baseline voltage values for a plurality of bit-planes;

measuring a first phase ripple value of a display using the baseline voltage values;

generating a modified bit-plane sequence by adding a voltage offset to at least one baseline voltage value of at least one bit-plane of the plurality of bit-planes of a first bit-plane sequence of the plurality of bit-plane sequences;

measuring a second phase ripple value of the display using the modified bit-plane sequence; and

selecting between the first bit-plane sequence and the modified bit-plane sequence based on comparing the first and second phase ripple values.

15 . The method of claim 14 , wherein:

DC-balance is maintained by applying equal and opposite voltage offsets to corresponding bit-planes in positive and negative polarity sub-frames.

16 . The method of claim 14 , further comprising:

receiving voltage control commands; and

generating pixel electrode voltages for the display according to the voltage values of the selected first bit-plane sequence or modified bit-plane sequence.

17 . The method of claim 14 , wherein:

the voltage offset is between 0.1V and 0.2V.

18 . The method of claim 14 , wherein:

each bit-plane sequence includes one or more groups of 1-values spaced apart from one another within the bit-plane sequence by one or more groups of 0-values.

19 . The method of claim 18 , wherein:

each of the one or more groups of 1-values has a respective number of bit-planes that is within one bit-plane of the respective number of bit-planes of each other group of 1-values.

20 . The method of claim 19 , wherein:

each of the one or more groups of 0-values has a respective number of bit-planes that is within one bit-plane of the respective number of bit-planes of each other group of 0-values.