Ballast circuit for stabilizing supply voltages in high-speed circuits
According to an embodiment, a system includes a writer circuit of a pre-amplifier coupled between first and second pre-amplifier supply voltages and configured to generate a write current. A ballast circuit couples in parallel with the writer circuit between first and second supply voltages. The ballast circuit generates first and second ballast currents in response to a write enable signal and injects them into the pre-amplifier supply voltages to pre-charge parasitic inductances before the writer circuit generates the write current. The ballast circuit includes a programmable delay circuit that generates a timing pulse matching a propagation delay of the writer circuit, and a configurable current mirror circuit that generates the ballast currents. The ballast currents are de-asserted when the writer circuit begins generating the write current.
1 . A system, comprising:
a writer circuit of a pre-amplifier, the writer circuit coupled between a first pre-amplifier supply voltage and a second pre-amplifier supply voltage and configured to generate a write current; and
a ballast circuit coupled in parallel with the writer circuit, the ballast circuit coupled between a first supply voltage and a second supply voltage and configured to:
generate first and second ballast currents in response to a write enable signal,
inject the first and second ballast currents into the first and second pre-amplifier supply voltages to pre-charge parasitic inductances before the writer circuit generates the write current, and
de-assert the first and second ballast currents in response to the writer circuit generating the write current.
2 . The system of claim 1 , wherein the ballast circuit comprises:
a programmable delay circuit configured to generate a timing pulse having a duration matching a propagation delay of the writer circuit; and
a configurable current mirror circuit configured to generate the first and second ballast currents in response to the timing pulse.
3 . The system of claim 2 , wherein the configurable current mirror circuit comprises a plurality of selectable transistors configured to adjust amplitudes of the first and second ballast currents based on stored selection bits.
4 . The system of claim 2 , wherein the programmable delay circuit comprises circuitry matching the writer circuit to replicate the propagation delay.
5 . The system of claim 1 , wherein the first supply voltage and the second supply voltage are generated by a power supply circuit, and wherein the first pre-amplifier supply voltage and the second pre-amplifier supply voltage are derived from the first supply voltage and the second supply voltage through a flex circuit.
6 . The system of claim 1 , wherein the writer circuit comprises:
a plurality of logic chains configured to receive differential data; and
an output stage coupled to the plurality of logic chains and configured to generate the write current based on the differential data.
7 . The system of claim 1 , wherein the ballast circuit is configured to monitor bit error rates of data written by the writer circuit and adjust amplitudes of the first and second ballast currents based on the monitored bit error rates.
8 . A method, comprising:
generating first and second ballast currents from a first supply voltage and a second supply voltage in response to a write enable signal;
injecting the first and second ballast currents into first and second pre-amplifier supply voltages to pre-charge parasitic inductances before a writer circuit of a pre-amplifier generates a write current, wherein the writer circuit is coupled between the first pre-amplifier supply voltage and the second pre-amplifier supply voltage; and
de-asserting the first and second ballast currents in response to the writer circuit generating the write current.
9 . The method of claim 8 , wherein generating the first and second ballast currents comprises:
generating a timing pulse having a duration matching a propagation delay of the writer circuit; and
generating the first and second ballast currents using a configurable current mirror circuit in response to the timing pulse.
10 . The method of claim 9 , wherein generating the timing pulse comprises implementing matching circuitry to replicate the propagation delay of the writer circuit.
11 . The method of claim 9 , wherein generating the first and second ballast currents comprises adjusting amplitudes of the first and second ballast currents using selectable transistors in the configurable current mirror circuit based on stored selection bits.
12 . The method of claim 8 , wherein:
the first supply voltage and the second supply voltage are generated by a power supply circuit; and
the first pre-amplifier supply voltage and the second pre-amplifier supply voltage are derived from the first supply voltage and the second supply voltage through a flex circuit.
13 . The method of claim 8 , further comprising:
monitoring bit error rates of data written by the writer circuit; and
adjusting amplitudes of the first and second ballast currents based on the monitored bit error rates.
14 . The method of claim 8 , wherein the writer circuit receives differential data through a plurality of logic chains and generates the write current based on the differential data using an output stage.
15 . A ballast circuit, comprising:
a programmable delay circuit configured to:
receive a write enable signal, and
generate a timing pulse having a duration matching a propagation delay of a writer circuit; and
a configurable current mirror circuit coupled between a first supply voltage and a second supply voltage, the configurable current mirror circuit configured to:
generate first and second ballast currents in response to the timing pulse,
inject the first and second ballast currents into first and second pre-amplifier supply voltages to pre-charge parasitic inductances before the writer circuit generates a write current, and
de-assert the first and second ballast currents in response to the writer circuit generating the write current.
16 . The ballast circuit of claim 15 , wherein the configurable current mirror circuit comprises:
a first set of selectable transistors coupled between the first supply voltage and a base node;
a second set of selectable transistors coupled between the base node and the second supply voltage; and
a reference current source coupled to the first and second sets of selectable transistors.
17 . The ballast circuit of claim 16 , further comprising a memory configured to store selection bits for controlling the first and second sets of selectable transistors to adjust amplitudes of the first and second ballast currents.
18 . The ballast circuit of claim 15 , further comprising a capacitor coupled between an output of the programmable delay circuit and the configurable current mirror circuit.
19 . The ballast circuit of claim 15 , wherein the programmable delay circuit comprises matching circuitry configured to replicate the propagation delay of the writer circuit.
20 . The ballast circuit of claim 15 , further comprising a monitoring circuit configured to:
monitor bit error rates of data written by the writer circuit, and
adjust the configurable current mirror circuit based on the monitored bit error rates.