Magnetoresistive random-access memory (MRAM) cell and method of operation thereof
An exemplary magnetoresistive random-access memory (MRAM) cell is configured to store more than one bit. The MRAM cell includes a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel. The first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter. The MRAM cell further includes a transistor connected to the first MTJ and the second MTJ, a bit line connected to the first MTJ and the second MTJ, a word line connected to the transistor, and a source line connected to the transistor. A method of writing to the MRAM cell can include supplying one or more write voltages to the MRAM cell (e.g., having different levels) depending on an initial memory state and a desired memory state of the MRAM cell.
1 . A magnetoresistive random-access memory (MRAM) cell configured to store more than one bit, the MRAM cell comprising:
a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel, wherein the first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter;
a transistor connected to the first MTJ and the second MTJ;
a bit line connected to the first MTJ and the second MTJ;
a word line and a source line connected to the transistor;
wherein the first MTJ has a first high resistance and a first low resistance and the second MTJ has a second high resistance and a second low resistance;
wherein the first MTJ and the second MTJ are configured to provide the second high resistance greater than the second low resistance, the second low resistance greater than the first high resistance, and the first high resistance greater than the first low resistance ; and
wherein:
the first MTJ and the second MTJ are configured to provide the first low resistance and the second low resistance, respectively, upon application of a first positive write voltage to the MRAM cell,
the first MTJ and the second MTJ are configured to provide the first low resistance and the second high resistance, respectively, upon application of a second positive write voltage to the MRAM cell, wherein the second positive write voltage and the first positive write voltage are different,
the first MTJ and the second MTJ are configured to provide the first high resistance and the second low resistance, respectively, upon application of a first negative write voltage to the MRAM cell, and
the first MTJ and the second MTJ are configured to provide the first high resistance and the second high resistance, respectively, upon application of a second negative write voltage to the MRAM cell, wherein the second negative write voltage and the first negative write voltage are different.
2 . The MRAM cell of claim 1 , wherein the first MTJ and the second MTJ are in a same column of an MRAM cell array, the first MTJ is in a first row of the MRAM cell array, and the second MTJ is in a second row of the MRAM cell array.
3 . The MRAM cell of claim 1 , wherein the first positive write voltage is greater than the second positive write voltage, and the first negative write voltage is greater than the second negative write voltage.
4 . The MRAM cell of claim 1 , wherein the transistor is a fin-like field effect transistor.
5 . The MRAM cell of claim 1 , wherein:
the first MTJ includes a first free layer, a first pinned layer, and a first tunneling barrier layer disposed between the first free layer and the first pinned layer;
the second MTJ includes a second free layer, a second pinned layer, and a second tunneling barrier layer disposed between the second free layer and the second pinned layer;
the first free layer and the second free layer are connected to the bit line; and
the first pinned layer and the second pinned layer are connected to the transistor.
6 . The MRAM cell of claim 1 , wherein:
a ratio of the second diameter to the first diameter is at least 0.5; and
the ratio of the second diameter to the first diameter is less than 1.0.
7 . The MRAM cell of claim 1 , wherein the first MTJ has a first configuration of layers, the second MTJ has a second configuration of layers, and the first configuration of layers is the same as the second configuration of layers.
8 . The MRAM cell of claim 1 , wherein the first MTJ has a first configuration of layers, the second MTJ has a second configuration of layers, and the first configuration of layers is different than the second configuration of layers.
9 . The MRAM cell of claim 1 , wherein the transistor is a front-end-of-line structure and the first MTJ and the second MTJ are back-end-of-line structures.
10 . A nonvolatile memory structure comprising:
a plurality of magnetoresistive random-access memory (MRAM) cells, wherein each of the plurality of MRAM cells includes:
a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel, wherein the first MTJ and the second MTJ are connected to a respective bit line, the first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter, and
a transistor connected to the first MTJ and the second MTJ, wherein the transistor is connected to a respective word line and a respective source line; and
wherein first MTJs and second MTJs of the plurality of MRAM cells are arranged to provide first rows having a first MTJ-second MTJ pattern and second rows having a second MTJ-first MTJ pattern, wherein the first rows interleave the second rows.
11 . The nonvolatile memory structure of claim 10 , wherein the first MTJs and the second MTJs of the plurality of MRAM cells are further arranged to provide first columns having the first MTJ-second MTJ pattern and second columns having the second MTJ-first MTJ pattern, wherein the first columns interleave the second columns.
12 . The nonvolatile memory structure of claim 10 , wherein:
for each of the plurality of MRAM cells, each of the first MTJ and the second MTJ has a high resistance state and a low resistance state;
the first MTJ has a first resistance when in the high resistance state and a second resistance when in the low resistance state;
the second MTJ has a third resistance when in the high resistance state and a fourth resistance when in the low resistance state; and
the first resistance, the second resistance, the third resistance, and the fourth resistance are different.
13 . The nonvolatile memory structure of claim 12 , wherein the third resistance is greater than the fourth resistance, the fourth resistance is greater than the first resistance, and the first resistance is greater than the second resistance.
14 . The nonvolatile memory structure of claim 10 , wherein transistors of a group of the plurality of MRAM cells are connected to a same source line.
15 . The nonvolatile memory structure of claim 10 , wherein:
a ratio of the second diameter to the first diameter is at least 0.5; and
the ratio of the second diameter to the first diameter is less than 1.0.
16 . A magnetoresistive random-access memory (MRAM) cell configured to store more than one bit, the MRAM cell comprising:
a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel, wherein the first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter;
a bit line and a source line, wherein the bit line is connected to a first terminal of the first MTJ and the second MTJ and the source line is connected to a second terminal of the first MTJ and the second MTJ, and further wherein the bit line and the source line are configured for application of a write voltage therebetween, wherein the write voltage includes a first negative voltage, a second negative voltage, a first positive voltage, and a second positive voltage;
wherein each of the first MTJ and the second MTJ has a high resistance state and a low resistance state, the first MTJ has a first resistance when in the high resistance state and a second resistance when in the low resistance state, and the second MTJ has a third resistance when in the high resistance state and a fourth resistance when in the low resistance state;
wherein the first resistance, the second resistance, the third resistance, and the fourth resistance are different; and
wherein:
when the first MTJ is in the low resistance state and the second MTJ is in the low resistance state, the first MTJ is configured to enter the high resistance state upon application of the first negative voltage,
when the first MTJ is in the high resistance state and the second MTJ is in the low resistance state, the second MTJ is configured to enter the high resistance state upon application of the second negative voltage, wherein the second negative voltage is less than the first negative voltage,
when the first MTJ is in the high resistance state and the second MTJ is in the high resistance state, the first MTJ is configured to enter the low resistance state upon application of the first positive voltage, and
when the first MTJ is in the low resistance state and the second MTJ is in the high resistance state, the second MTJ is configured to enter the low resistance state upon application of the second positive voltage, wherein the second positive voltage is greater than the first positive voltage.
17 . The MRAM cell of claim 16 , wherein a ratio of the second diameter to the first diameter is about 0.8 to about 0.9.
18 . The MRAM cell of claim 16 , wherein each of the first diameter and the second diameter is less than about 100 nm.
19 . The MRAM cell of claim 16 , wherein the first MTJ and the second MTJ are in a same column of an MRAM cell array, the first MTJ is in a first row of the MRAM cell array, and the second MTJ is in a second row of the MRAM cell array.
20 . The MRAM cell of claim 16 , wherein the first MTJ and the second MTJ are disposed within a multilayer interconnect structure disposed over a device substrate.