Memory devices including ferroelectric cell capacitors and operating methods thereof
A memory device including a ferroelectric cell capacitor, and an operating method thereof. For example, an operating method of a memory device, according to some embodiments, may include pre-charging a bit line to a pre-charge voltage, the bit line connected to a ferroelectric cell capacitor to be written to, writing data into the ferroelectric cell capacitor by adjusting a level of a voltage applied to a bit line and a word line corresponding to the ferroelectric cell capacitor, and deactivating the word line, wherein a voltage applied to a plate line connected to the ferroelectric cell capacitor is maintained at a ground voltage during the writing of the data into the ferroelectric cell capacitor.
1 . An operating method of a memory device, the method comprising:
pre-charging a bit line to a pre-charge voltage, the bit line connected to a ferroelectric cell capacitor to be written to;
writing data into the ferroelectric cell capacitor by adjusting a level of a voltage applied to the bit line and to a word line corresponding to the ferroelectric cell capacitor; and
deactivating the word line,
wherein a voltage applied to a plate line connected to the ferroelectric cell capacitor is maintained at a ground voltage during the writing of the data into the ferroelectric cell capacitor.
2 . The method of claim 1 , wherein the writing of the data comprises applying a first driving voltage to the word line.
3 . The method of claim 1 , wherein the writing of the data comprises:
when writing first data to the ferroelectric cell capacitor, applying a second driving voltage to the bit line; and
when writing second data to the ferroelectric cell capacitor, applying a third driving voltage to the bit line.
4 . The method of claim 3 ,
wherein the second driving voltage is a positive voltage, and the third driving voltage is a negative voltage.
5 . The method of claim 3 ,
wherein the third driving voltage is a reverse voltage of the second driving voltage, which has an equal magnitude to the second driving voltage but has an opposite sign to the second driving voltage.
6 . An operating method of a memory device, the method comprising:
pre-charging a bit line to a pre-charge voltage, the bit line connected to a ferroelectric cell capacitor to be read;
reading data stored in the ferroelectric cell capacitor by performing a charge sharing operation;
rewriting the data into the ferroelectric cell capacitor by adjusting a level of a voltage applied to the bit line; and
deactivating a word line corresponding to the ferroelectric cell capacitor,
wherein a voltage applied to a plate line connected to the ferroelectric cell capacitor is maintained at a ground voltage during the reading of the data stored in the ferroelectric cell capacitor.
7 . The method of claim 6 , wherein the rewriting of the data comprises applying a first driving voltage to the word line.
8 . The method of claim 6 , wherein the reading of the data comprises:
when reading first data from the ferroelectric cell capacitor in which the first data is stored, sensing a first sense voltage on the bit line; and
when reading second data from the ferroelectric cell capacitor in which the second data is stored, sensing a second sense voltage on the bit line.
9 . The method of claim 8 ,
wherein the first sense voltage is a positive voltage, and the second sense voltage is a negative voltage.
10 . The method of claim 6 , wherein the rewriting of the data comprises:
when first data is read from the ferroelectric cell capacitor in which the first data is stored, applying a second driving voltage to the bit line; and
when second data is read from the ferroelectric cell capacitor in which the second data is stored, applying a third driving voltage to the bit line.
11 . The method of claim 10 , wherein the second driving voltage is a positive voltage, and the third driving voltage is a negative voltage.
12 . The method of claim 10 , wherein the third driving voltage is a reverse voltage of the second driving voltage, which has the same magnitude as the second driving voltage but has an opposite sign to the second driving voltage.
13 . A memory device comprising:
a memory cell array including a first layer including a plurality of first ferroelectric cell capacitors and a second layer including a plurality of second ferroelectric cell capacitors;
a first bit line decoder connected to the first layer;
a second bit line decoder connected to the second layer;
a common plate line connected to the first layer and the second layer; and
a word line decoder connected to the first layer and the second layer,
wherein the memory device is configured to apply a voltage to the common plate line that is maintained at a ground voltage when a write operation or a read operation is performed on the memory cell array.
14 . The memory device of claim 13 , further comprising control circuitry that is configured to write first data to a first ferroelectric cell capacitor of the plurality of first ferroelectric cell capacitors and write second data to a second ferroelectric cell capacitor of the plurality of second ferroelectric cell capacitors by adjusting output voltages of the first bit line decoder and the second bit line decoder.
15 . The memory device of claim 13 , further comprising control circuitry, wherein the control circuitry is configured to:
output a first signal to the first bit line decoder configured to cause pre-charging of a bit line to a pre-charge voltage, the bit line connected to a first ferroelectric cell capacitor of the plurality of first ferroelectric cell capacitors, the first ferroelectric cell capacitor to be written,
output a second signal that is configured to cause the first bit line decoder to adjust of a level of a voltage applied to the bit line connected to the first ferroelectric cell capacitor, and output a third signal that is configured to cause the word line decoder to adjust a level of a voltage applied to a word line connected to the first ferroelectric cell capacitor, thereby allowing data to be written into the first ferroelectric cell capacitor, and
output a fourth signal that is configured to cause the word line decoder to deactivate the word line.
16 . The memory device of claim 15 ,
wherein the control circuitry is configured to:
apply a second driving voltage to the bit line when writing first data to the first ferroelectric cell capacitor, and
apply a third driving voltage to the bit line when writing second data to the first ferroelectric cell capacitor.
17 . The memory device of claim 16 ,
wherein the second driving voltage is a positive voltage, and the third driving voltage is a negative voltage.
18 . The memory device of claim 16 ,
wherein the third driving voltage is a reverse voltage of the second driving voltage, which has the same magnitude as the second driving voltage.
19 . The memory device of claim 13 , further comprising a bit line sense amplifier and control circuitry,
wherein the control circuitry is configured to:
output a first signal configured to cause the first bit line decoder to pre-charge a bit line to a pre-charge voltage, the bit line connected to a first ferroelectric cell capacitor of the plurality of first ferroelectric cell capacitors, the first ferroelectric cell capacitor to be read,
read data stored in the first ferroelectric cell capacitor by causing the bit line sense amplifier to perform a charge sharing operation,
output a second signal configured to cause the first bit line decoder to adjust a level of a voltage applied to the bit line connected to the first ferroelectric cell capacitor, thereby allowing the data to be rewritten into the first ferroelectric cell capacitor, and
output a third signal configured to cause the word line decoder to deactivate a word line corresponding to the first ferroelectric cell capacitor.
20 . The memory device of claim 19 ,
wherein the control circuitry, which allows the data to be rewritten, is configured to:
when first data is read from the first ferroelectric cell capacitor in which the first data is stored, apply a second driving voltage to the bit line; and
when second data is read from the first ferroelectric cell capacitor in which the second data is stored, apply a third driving voltage to the bit line,
wherein the third driving voltage is a reverse voltage of the second driving voltage, which has an equal magnitude to the second driving voltage but has an opposite sign to the second driving voltage.