IP Library › Granted Patent US 12682941
Granted Patent B2
US 12682941 · App. 18/646,415 · Granted Jul 14, 2026

Semiconductor device comprising 3D-memory

Inventors: Tomoaki Atsumi (Hadano, JP); Junpei Sugao (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G11C11/4094G11C11/401G11C11/4096G11C11/4097H10D30/6731H10D30/6745H10D30/6755H10D30/6757H10D86/423H10D86/441H10D86/471H10D86/481H10D86/60H10B10/12H10B41/70
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Quick Facts
Patent No.
US 12682941
App. No.
18/646,415
Granted
Jul 14, 2026
Kind
B2
Abstract

The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

Claims (86)

1 . A semiconductor device comprising:

a plurality of first transistors;

a plurality of second transistors; and

a plurality of first capacitors,

wherein a first transistor of the plurality of first transistors is provided over a second transistor of the plurality of first transistors,

wherein a first transistor of the plurality of second transistors is provided over a second transistor of the plurality of second transistors,

wherein a first insulator is provided over the second transistor of the plurality of first transistors,

wherein a first semiconductor is provided over the first insulator,

wherein the first semiconductor comprises a region configured to function as a channel formation region of the first transistor of the plurality of first transistors,

wherein a first conductor is provided over the first insulator and the first semiconductor,

wherein the first conductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of first transistors, a second region configured to function as a gate electrode of the first transistor of the plurality of second transistors, and a third region configured to function as a first electrode of one capacitor of the plurality of first capacitors,

wherein a second insulator is provided over the first conductor,

wherein a second conductor is provided over the second insulator,

wherein the second conductor comprises a region configured to function as a second electrode of the one capacitor of the plurality of first capacitors, and

wherein a second semiconductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of second transistors, a second region configured to function as a channel formation region of the first transistor of the plurality of second transistors, a third region configured to function as the other of the source electrode and the drain electrode of the first transistor of the plurality of second transistors, a fourth region configured to function as one of a source electrode and a drain electrode of the second transistor of the plurality of second transistors, and a fifth region configured to function as a channel formation region of the second transistor of the plurality of second transistors.

2 . A semiconductor device comprising:

a plurality of first transistors;

a plurality of second transistors; and

a plurality of first capacitors,

wherein a first transistor of the plurality of first transistors is provided over a second transistor of the plurality of first transistors,

wherein a first transistor of the plurality of second transistors is provided over a second transistor of the plurality of second transistors,

wherein a first insulator is provided over the second transistor of the plurality of first transistors,

wherein a first semiconductor is provided over the first insulator,

wherein the first semiconductor comprises a region configured to function as a channel formation region of the first transistor of the plurality of first transistors,

wherein a first conductor is provided over the first insulator and the first semiconductor,

wherein the first conductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of first transistors, a second region configured to function as a gate electrode of the first transistor of the plurality of second transistors, and a third region configured to function as a first electrode of one capacitor of the plurality of first capacitors,

wherein a second insulator is provided over the first conductor,

wherein a second conductor is provided over the second insulator,

wherein the second conductor comprises a region configured to function as a second electrode of the one capacitor of the plurality of first capacitors,

wherein a second semiconductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of second transistors, a second region configured to function as a channel formation region of the first transistor of the plurality of second transistors, a third region configured to function as the other of the source electrode and the drain electrode of the first transistor of the plurality of second transistors, a fourth region configured to function as one of a source electrode and a drain electrode of the second transistor of the plurality of second transistors, and a fifth region configured to function as a channel formation region of the second transistor of the plurality of second transistors, and

wherein the first semiconductor comprises an oxide semiconductor including indium.

3 . A semiconductor device comprising:

a plurality of first transistors;

a plurality of second transistors; and

a plurality of first capacitors,

wherein a first transistor of the plurality of first transistors is provided over a second transistor of the plurality of first transistors,

wherein a first transistor of the plurality of second transistors is provided over a second transistor of the plurality of second transistors,

wherein a first insulator is provided over the second transistor of the plurality of first transistors,

wherein a first semiconductor is provided over the first insulator,

wherein the first semiconductor comprises a region configured to function as a channel formation region of the first transistor of the plurality of first transistors,

wherein a first conductor is provided over the first insulator and the first semiconductor,

wherein the first conductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of first transistors, a second region configured to function as a gate electrode of the first transistor of the plurality of second transistors, and a third region configured to function as a first electrode of one capacitor of the plurality of first capacitors,

wherein a second insulator is provided over the first conductor,

wherein a second conductor is provided over the second insulator,

wherein the second conductor comprises a region configured to function as a second electrode of the one capacitor of the plurality of first capacitors,

wherein a second semiconductor comprises a first region configured to function as one of a source electrode and a drain electrode of the first transistor of the plurality of second transistors, a second region configured to function as a channel formation region of the first transistor of the plurality of second transistors, a third region configured to function as the other of the source electrode and the drain electrode of the first transistor of the plurality of second transistors, a fourth region configured to function as one of a source electrode and a drain electrode of the second transistor of the plurality of second transistors, and a fifth region configured to function as a channel formation region of the second transistor of the plurality of second transistors,

wherein the first semiconductor comprises an oxide semiconductor including indium,

wherein the second semiconductor comprises silicon,

wherein, in a cross-sectional view, the first semiconductor extends in a first direction parallel to a substrate over which the plurality of first transistors and the plurality of second transistors are formed, and

wherein, in the cross-sectional view, the second semiconductor extends in a second direction perpendicular to the substrate.

4 . The semiconductor device according to claim 1 , further comprising:

a third insulator,

wherein the third insulator comprises a first region configured to function as a first gate insulating film of the first transistor of the plurality of second transistors and a second region configured to function as a second gate insulating film of the second transistor of the plurality of second transistors, and

wherein the third insulator and the second semiconductor are provided in a first opening of the first insulator, a second opening of the first conductor, and a third opening in the second insulator.

5 . The semiconductor device according to claim 2 , further comprising:

a third insulator,

wherein the third insulator comprises a first region configured to function as a first gate insulating film of the first transistor of the plurality of second transistors and a second region configured to function as a second gate insulating film of the second transistor of the plurality of second transistors, and

wherein the third insulator and the second semiconductor are provided in a first opening of the first insulator, a second opening of the first conductor, and a third opening of the second insulator.

6 . The semiconductor device according to claim 3 , further comprising:

a third insulator,

wherein the third insulator comprises a first region configured to function as a first gate insulating film of the first transistor of the plurality of second transistors and a second region configured to function as a second gate insulating film of the second transistor of the plurality of second transistors, and

wherein the third insulator and the second semiconductor are provided in a first opening of the first insulator, a second opening of the first conductor, and a third opening of the second insulator.

7 . The semiconductor device according to claim 1 , further comprising:

a third insulator,

wherein the third insulator comprises a first region configured to function as a first gate insulating film of the first transistor of the plurality of second transistors and a second region configured to function as a second gate insulating film of the second transistor of the plurality of second transistors, and

wherein the third insulator and the second semiconductor are provided in a first cylindrical opening of the first insulator, a second cylindrical opening of the first conductor, and a third cylindrical opening of the second insulator.

8 . The semiconductor device according to claim 2 , further comprising:

a third insulator,

wherein the third insulator comprises a first region configured to function as a first gate insulating film of the first transistor of the plurality of second transistors and a second region configured to function as a second gate insulating film of the second transistor of the plurality of second transistors, and

wherein the third insulator and the second semiconductor are provided in a first cylindrical opening of the first insulator, a second cylindrical opening of the first conductor, and a third cylindrical opening of the second insulator.

9 . The semiconductor device according to claim 3 , further comprising:

a third insulator,

wherein the third insulator comprises a first region configured to function as a first gate insulating film of the first transistor of the plurality of second transistors and a second region configured to function as a second gate insulating film of the second transistor of the plurality of second transistors, and

wherein the third insulator and the second semiconductor are provided in a first cylindrical opening of the first insulator, a second cylindrical opening of the first conductor, and a third cylindrical opening of the second insulator.

10 . The semiconductor device according to claim 1 , further comprising:

a plurality of third transistors,

wherein a channel formation region of one of the plurality of third transistors is provided in a substrate over which the plurality of first transistors and the plurality of second transistors are formed, and

wherein one of a source electrode and a drain electrode of the one of the plurality of third transistors is electrically connected to the other of the source electrode and the drain electrode of the second transistor of the plurality of second transistors.

11 . The semiconductor device according to claim 2 , further comprising:

a plurality of third transistors,

wherein a channel formation region of one of the plurality of third transistors is provided in a substrate over which the plurality of first transistors and the plurality of second transistors are formed, and

wherein one of a source electrode and a drain electrode of the one of the plurality of third transistors is electrically connected to the other of the source electrode and the drain electrode of the second transistor of the plurality of second transistors.

12 . The semiconductor device according to claim 3 , further comprising:

a plurality of third transistors,

wherein a channel formation region of one of the plurality of third transistors is provided in the substrate, and

wherein one of a source electrode and a drain electrode of the one of the plurality of third transistors is electrically connected to the other of the source electrode and the drain electrode of the second transistor of the plurality of second transistors.