Memory system applying read voltage for reading data with small number of fail bits

1 . A memory system comprising:

a non-volatile memory including a plurality of blocks each including a plurality of memory cells; and

a memory controller configured to execute a first read process of reading data from a first memory cell in a first block by using a first read voltage and a second read process of reading data from a second memory cell in the first block by using a second read voltage, wherein

the memory controller is configured to:

maintain, in a case where a first condition is satisfied, a difference between the first read voltage and the second read voltage at a first value, and change both the first read voltage and the second read voltage; and

change, in a case where a second condition is satisfied after the first condition has been satisfied, a difference between the first read voltage and the second read voltage from the first value to a second value different from the first value, and change at least one of the first read voltage and the second read voltage,

the first condition is a first sub-condition, a second sub-condition, or a third sub-condition,

in a case where the first condition is the first sub-condition, the second condition is a fourth sub-condition, a fifth sub-condition, or a sixth sub-condition,

in a case where the first condition is the second sub-condition or the third sub-condition, the second condition is the fifth sub-condition or the sixth sub-condition,

the first sub-condition is that a first period elapses after data is written to the first memory cell and the second memory cell,

the second sub-condition is that the memory controller executes the first read process independently of an instruction from an external host,

the third sub-condition is that data including fail bits greater than or equal to a second threshold is read from the first block,

the fourth sub-condition is that a second period longer than the first period elapses after data is written to the first memory cell and the second memory cell,

the fifth sub-condition is that data is read from the first block after the difference is maintained at the first value and both the first read voltage and the second read voltage are changed, and

the sixth sub-condition is that data including fail bits greater than or equal to a first threshold is read from the first block after the difference is maintained at the first value and both the first read voltage and the second read voltage are changed.

2 . The memory system according to claim 1 , wherein:

the non-volatile memory includes a second block including a third memory cell and a fourth memory cell; and

the memory controller is configured to:

execute a third read process of reading data from the third memory cell by using a third read voltage, and a fourth read process of reading data from the fourth memory cell by using a fourth read voltage, and

change a difference between the third read voltage and the fourth read voltage from a third value to a fourth value different from the third value, and change at least one of the third read voltage and the fourth read voltage, and

a difference between the first value and the second value is different from a difference between the third value and the fourth value.

3 . The memory system according to claim 2 , wherein the memory controller is configured to independently execute changing at least one of the first read voltage and the second read voltage and changing at least one of the third read voltage and the fourth read voltage.

4 . The memory system according to claim 2 , wherein the memory controller is configured to independently execute changing both the first read voltage and the second read voltage and changing both the third read voltage and the fourth read voltage.

5 . The memory system according to claim 2 , wherein

the non-volatile memory further includes a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, a third word line coupled to the third memory cell, and a fourth word line coupled to the fourth memory cell,

the second word line is different from the first word line, and

the fourth word line is different from the third word line.

6 . The memory system according to claim 2 , wherein

each of the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell is configured to store data including a first bit and a second bit different from the first bit,

the first read process is a process of reading data of the first bit from the first memory cell by using the first read voltage,

the second read process is a process of reading data of the first bit from the second memory cell by using the second read voltage,

the third read process is a process of reading data of the first bit from the third memory cell by using the third read voltage, and

the fourth read process is a process of reading data of the first bit from the fourth memory cell by using the fourth read voltage.

7 . The memory system according to claim 1 , wherein

the non-volatile memory further includes a first word line coupled to the first memory cell and a second word line coupled to the second memory cell, and

the second word line is different from the first word line.

8 . The memory system according to claim 1 , wherein

the memory controller is configured to:

manage a plurality of tables each storing information indicating the difference between the first read voltage and the second read voltage; and

maintain the difference between the first read voltage and the second read voltage at the first value by using a first table of the plurality of tables.

9 . The memory system according to claim 8 , wherein

the memory controller is configured to change the difference between the first read voltage and the second read voltage to the second value by using a second table of the plurality of tables, and

the second table is different from the first table.

10 . The memory system according to claim 9 , wherein

the memory controller is configured to:

manage an initial voltage and a reference correction amount;

determine the first read voltage based on the initial voltage and the reference correction amount; and

change, in the case where the first condition is satisfied, the first read voltage by changing the reference correction amount.

11 . The memory system according to claim 1 , wherein

the memory controller is configured to:

manage an initial voltage and a reference correction amount;

determine the first read voltage based on the initial voltage and the reference correction amount;

manage a plurality of tables each storing information indicating the difference between the first read voltage and the second read voltage; and

determine the second read voltage by using one of the plurality of tables.

12 . The memory system according to claim 11 , wherein

the memory controller is configured to:

determine, before the first condition is satisfied, the second read voltage by using a first table of the plurality of tables; and

in the case where the first condition is satisfied:

change the first read voltage by changing the reference correction amount; and

maintain the difference between the first read voltage and the second read voltage at the first value by using the first table.

13 . The memory system according to claim 12 , wherein

the memory controller is configured to change, in the case where the second condition is satisfied, the difference between the first read voltage and the second read voltage to the second value by using a second table of the plurality of tables, and

the second table is different from the first table.

14 . The memory system according to claim 1 , wherein

each of the first memory cell and the second memory cell is configured to store data including a first bit and a second bit different from the first bit,

the first read process is a process of reading data of the first bit from the first memory cell by using the first read voltage, and

the second read process is a process of reading data of the first bit from the second memory cell by using the second read voltage.

15 . The memory system according to claim 14 , wherein

the memory controller is configured to execute a fifth read process of reading data of the second bit from the first memory cell by using a fifth read voltage and a sixth read process of reading data of the second bit from the second memory cell by using a sixth read voltage.

16 . The memory system according to claim 15 , wherein

the fifth read voltage is different from the first read voltage, and

the sixth read voltage is different from the second read voltage.