Hybrid boosting for memory write assist
A memory is provided that includes a negative bit line hybrid boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The hybrid boost circuit uses a charged gate capacitance of a boost transistor and a charged capacitance of a metal line capacitor to provide the negative bit line boost. Similarly, the memory may include a word line hybrid boost circuit that uses another boost transistor and another metal line capacitor for boosting a word line above a word line power supply voltage during the write operation.
1 . A memory comprising:
a bit line;
a negative bit line hybrid boost circuit including:
a boost transistor; and
a metal line capacitor including a first metal line and an at least one second metal line extending adjacent to the first metal line, wherein the first metal line is coupled to the bit line and to a gate of the boost transistor, and wherein the at least one second metal line is coupled to a drain and source of the boost transistor,
wherein the bit line is within a first metal layer neighboring a semiconductor substrate, and wherein the first metal line and the at least one second metal line is within a second metal layer neighboring the first metal layer.
2 . The memory of claim 1 , wherein a length of the metal line capacitor is proportional to a length of the bit line.
3 . The memory of claim 2 , wherein the length of the metal line capacitor is substantially equal to the length of the bit line.
4 . The memory of claim 1 , wherein the negative bit line hybrid boost circuit further includes:
a first transistor having a drain coupled to the first metal line and having a source coupled to ground; and
a first inverter configured to invert a boost signal and having an output terminal coupled to a gate of the first transistor.
5 . A memory comprising:
a bit line;
a negative bit line hybrid boost circuit including:
a boost transistor;
a metal line capacitor including a first metal line and an at least one second metal line extending adjacent to the first metal line, wherein the first metal line is coupled to the bit line and to a gate of the boost transistor, and wherein the at least one second metal line is coupled to a drain and source of the boost transistor;
a first transistor having a drain coupled to the first metal line and having a source coupled to ground;
a first inverter configured to invert a boost signal and having an output terminal coupled to a gate of the first transistor;
a second inverter in series with the first inverter; and
a third inverter in series with the second inverter and having an output terminal coupled to the at least one second metal line and to the source and the drain of the boost transistor.
6 . The memory of claim 5 , wherein the boost transistor comprises a p-type metal-oxide semiconductor (PMOS) transistor.
7 . The memory of claim 1 , further comprising:
a write driver; and
a column multiplexer, wherein the bit line is configured to couple through the column multiplexer and the write driver to the negative bit line hybrid boost circuit.
8 . The memory of claim 1 , wherein the memory is a static random-access memory (SRAM).
9 . The memory of claim 1 , further comprising:
an array of bitcells arranged into columns and rows, wherein the bit line is configured to extend across one of the columns.
10 . The memory of claim 1 , wherein the memory is incorporated into a cellular telephone.
11 . The memory of claim 1 , wherein the at least one second metal line comprises a third metal line extending adjacent a first side of the first metal line and comprises a fourth metal line extending adjacent a second side of the first metal line.