Semiconductor storage device for comparing reference voltages
A semiconductor storage device includes one or more first memory cells connected in parallel between a first voltage supply line supplying a first voltage and a second voltage supply line supplying a second voltage different from the first voltage, and one or more second memory cells connected in parallel between the second voltage supply line and a third voltage supply line supplying the first voltage, wherein each of the first memory cells includes a first storage element having a resistance value corresponding to a first status or a second status, and a first cell transistor connected between the first storage element and the first voltage supply line, and each of the second memory cells includes a second storage element having a resistance value corresponding to a first status or a second status, and a second cell transistor connected between the second storage element and the third voltage supply line.
1 . A semiconductor storage device, comprising:
at least one first memory cell of a plurality of first memory cells, wherein
the at least one first memory cell is connected in parallel between a first voltage supply line and a second voltage supply line,
the first voltage supply line supplies a first voltage, and
the second voltage supply line supplies a second voltage different from the first voltage; and
at least one second memory cell of a plurality of second memory cells, wherein
the at least one second memory cell is connected in parallel between the second voltage supply line and a third voltage supply line,
the third voltage supply line supplies the first voltage,
each of the plurality of first memory cells includes:
a first storage element having a first resistance value corresponding to one of a first status or a second status; and
a first cell transistor connected between the first storage element and the first voltage supply line, and
each of the plurality of second memory cells includes:
a second storage element having a second resistance value corresponding to one of the first status or the second status; and
a second cell transistor connected between the second storage element and the third voltage supply line;
a reference voltage generation unit configured to generate a reference voltage having a voltage level between a third voltage and a fourth voltage, wherein
the third voltage is generated based on a first biasing operation on each of the first storage element and the second storage element,
the first biasing operation on the each of the first storage element and the second storage element is based on:
the first voltage,
the second voltage,
the first resistance value of the first storage element that corresponds to the first status, and
the second resistance value of the second storage element that corresponds to the first status,
the fourth voltage is generated based on a second biasing operation on the each of the first storage element and the second storage element,
the second biasing operation on the each of the first storage element and the second storage element is based on;
the first voltage,
the second voltage,
the first resistance value of the first storage element that corresponds to the second status, and
the second resistance value of the second storage element that corresponds to the second status; and
a comparison unit configured to compare the reference voltage with a fifth voltage, wherein
the fifth voltage is generated based on a third biasing operation on one of the first storage element or the second storage element,
the third biasing operation on the one of the first storage element or the second storage element is biased based on each of the first voltage and the second voltage,
the reference voltage generation unit includes:
a first reference voltage generation unit that is connected between the first voltage supply line and the second voltage supply line, wherein the first reference voltage generation unit is configured to generate, based on a reading operation of the at least one second memory cell, the reference voltage; and
a second reference voltage generation unit that is connected between the second voltage supply line and the third voltage supply line, wherein
the second reference voltage generation unit is configured to generate, based on a reading operation of the at least one first memory cell, the reference voltage, and
the second voltage supply line is between the first reference voltage generation unit and the second reference voltage generation unit.
2 . The semiconductor storage device according to claim 1 , wherein a number of the plurality of first memory cells is equal to a number of the plurality of second memory cells.
3 . The semiconductor storage device according to claim 1 , wherein the second voltage supply line is between the at least one first memory cell and the at least one second memory cell.
4 . The semiconductor storage device according to claim 1 , further comprising:
a voltage supply unit configured to:
control, based on the reading operation of one of the at least one first memory cell or the at least one second memory cell, each of the first voltage supply line and the third voltage supply line to supply the first voltage;
control the second voltage supply line to supply the second voltage; and
stop the supply of the first voltage; and
a cell transistor control unit configured to turn on, based on the supply of the first voltage being stopped, one of the first cell transistor of the at least one first memory cell to be read or the second cell transistor of the at least one second memory cell to be read.
5 . The semiconductor storage device according to claim 4 , wherein the comparison unit is further configured to determine a potential difference between the first voltage and the second voltage, wherein
the potential difference corresponds to a difference in a voltage change rate between the first voltage supply line and the third voltage supply line, and
the potential difference is determined after the one of the first cell transistor or the second cell transistor is turned on.
6 . The semiconductor storage device according to claim 4 , wherein the second voltage supply line is fixed to the second voltage.
7 . The semiconductor storage device according to claim 1 , wherein
the first reference voltage generation unit includes:
a first reference resistance element; and
a first reference transistor that is connected between the first reference resistance element and the first voltage supply line, and
the second reference voltage generation unit includes:
a second reference resistance element; and
a second reference transistor that is connected between the second reference resistance element and the third voltage supply line.
8 . The semiconductor storage device according to claim 1 , wherein
the comparison unit is further configured to:
compare a sixth voltage of the first voltage supply line with a seventh voltage of the third voltage supply line; and
compare, based on the comparison of the sixth voltage of the first voltage supply line with the seventh voltage of the third voltage supply line, the reference voltage with the fifth voltage,
each of the sixth voltage and the seventh voltage is different from the first voltage, and
the semiconductor storage device further includes a comparison control unit configured to control the comparison unit to start the comparison of the reference voltage with the fifth voltage at a timing corresponding to the sixth voltage of the first voltage supply line and the seventh voltage of the third voltage supply line.
9 . The semiconductor storage device according to claim 8 , wherein the comparison control unit is further configured to:
control, based on the first voltage being higher than the second voltage, the comparison unit to start the comparison of the reference voltage with the fifth voltage at a timing at which one of the sixth voltage or the seventh voltage is lower than a first value, and
control, based on the first voltage being lower than the second voltage, the comparison unit to start the comparison of the reference voltage with the fifth voltage at a timing at which the one of the sixth voltage or the seventh voltage is higher than a second value.
10 . The semiconductor storage device according to claim 1 , wherein, in the reading operation of one of the at least one first memory cell or the at least one second memory cell, the first voltage is higher than the second voltage.
11 . The semiconductor storage device according to claim 10 , wherein
in a writing operation, the first voltage is lower than the second voltage, and
the second voltage obtained in the writing operation is higher than the first voltage obtained in the reading operation of the one of the at least one first memory cell or the at least one second memory cell.
12 . The semiconductor storage device according to claim 10 , wherein
in a writing operation, the first voltage is higher than the second voltage, and
the first voltage obtained in the writing operation is higher than the first voltage obtained in the reading operation of the one of the at least one first memory cell or the at least one second memory cell.
13 . The semiconductor storage device according to claim 1 , wherein, in the reading operation of one of the at least one first memory cell or the at least one second memory cell, the first voltage is lower than the second voltage.
14 . The semiconductor storage device according to claim 13 , wherein
in a writing operation, the first voltage is lower than the second voltage, and
the second voltage obtained in the writing operation is higher than the second voltage obtained in the reading operation of the one of the at least one first memory cell or the at least one second memory cell.